Commit Graph

187 Commits (1eb2860b4bd0306dddc5b2f2dc7403aa65c5e476)

Author SHA1 Message Date
Chris Wilson 23eeb7e1e4 intel: Detect cache domain inconsistency with valgrind
Every access to either the GTT or CPU pointer is supposed to be
proceeded by a set_domain ioctl so that GEM is able to manage the cache
domains correctly and for the following access to be coherent. Of
course, some people explicitly want incoherent, non-blocking access
which is going to trigger warnings by this patch but are probably better
served by explicit suppression.

v2: Also mark the pointers as inaccessible following the explicit unmap
and implicit unmap upon return to the cache.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-15 11:16:59 +00:00
Chris Wilson 90b23cc24c intel: Mark up with valgrind intrinsics to reduce false positives
In particular, declare the hidden CPU mmaps to valgrind so that it knows
about those memory regions.

v2: Add an additional VG_CLEAR for the getparam

References: https://bugs.freedesktop.org/show_bug.cgi?id=35071
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
[anholt: Ideally valgrind should just learn about the ioctls, and
         removing the clear for the non-valgrindified code feels risky.]
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-02-11 11:45:39 +00:00
Eugeni Dodonov 151cdcfe68 intel: query for LLC support
This adds support for querying the kernel about the LLC support in the
hardware.

In case the ioctl fails, we assume that it is present on GEN6 and GEN7.

v2: fix the return code checking

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-02-01 15:54:02 -02:00
Chad Versace 592ac67626 intel: Fix bufmgr_gem->gen for gen > 4
If the pci_device's actual gen was > 4, then we stupidly set
bufmgr_gem->gen = 6. Luckily this caused no bugs, and this fix shouldn't
change any behavior, because all checks against the gen currently have one
of the forms below:
    gen == 2
    gen == 3
    gen >= 4

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-01-30 13:03:35 -08:00
Eric Anholt b643b0713a intel: Add minimal decode for remaining gen7 packets in use.
This just gets packet name and length in place, with the remainder
unfinished.  I've long since finished the work that got me started
fixing up the decode.
2012-01-27 13:21:20 -08:00
Eric Anholt 54b12a085f intel: Add decode for gen7 constant buffer packets. 2012-01-27 13:21:20 -08:00
Eric Anholt 938df6be48 intel: Add decode for gen7 state pointers.
Since CC_STATE_POINTERS for gen6 and 7 are quite different but use the
same opcode, move gen6 out to a helper function too, so we can use a
helper function for gen7.
2012-01-27 13:21:20 -08:00
Eric Anholt 6a0b25e66b intel: Add support for parsing gen7 URB packets. 2012-01-27 13:21:20 -08:00
Eric Anholt ba8ce2da04 intel: Make most of the logic for 965 3d packet length checks table-driven.
This puts the error message in a consistent location relative to the
packet, and while I'm here I made the error message a bit more
informative.

Now, most static length packets need to just declare their length in
the table and not worry.
2012-01-27 13:21:20 -08:00
Eric Anholt b129e10af2 intel: Move the logic for getting 965 3d packet length to the packet table.
While I'm touching every line of the table, sort it by opcode.
2012-01-27 13:21:20 -08:00
Eric Anholt 3dcb2d47ee intel: Add support for parsing 965 3d packets using helper functions.
I want to add packets, without contributing to the switch statement of
doom.
2012-01-27 13:21:19 -08:00
Eric Anholt 5a1c10fe6a intel: Parse the correct length for gen7 3DSTATE_MULTISAMPLE. 2012-01-27 13:21:19 -08:00
Eric Anholt 9695eee8a2 intel: Put the "gen" shorthand chipset identifier in the context.
It's a lot nicer than using IS_WHATEVER(devid) all over the place, and
we have this in our other projects too.
2012-01-27 13:21:19 -08:00
Eric Anholt 028715ee70 intel: Avoid the need for most overflow checks by using a scratch page.
The overflow checks were all thoroughly untested, and a bunch of the
ones I'm deleting were pretty broken.  Now, in the case of overflow,
you just decode data of 0xd0d0d0d0, and instr_out prints the warning
message instead.  Note that this still has the same issue of being
under-tested, but at least it's one place instead of per-packet.

A couple of BUFFER_FAIL uses are left where the length to be decoded
could be (significantly) larger than a page, and the decode didn't
just call instr_out (which doesn't dereference data itself unless it's
safe).
2012-01-27 13:21:19 -08:00
Eric Anholt c1d2946da8 intel: Make instr_out take the decode context.
This reduces some of the extra derefs of the pointers.
2012-01-27 13:21:19 -08:00
Eric Anholt b0371612f4 intel: Use the context to simplify BR01 decode.
Similar to BR00, count was always 1 and was always an index, not a count.
2012-01-27 13:21:19 -08:00
Eric Anholt 62b410344c intel: Use the context to simplify BR00 decode.
The count (actually index) was always 0, because BR00 is dword 0.
2012-01-27 13:21:19 -08:00
Eric Anholt de49fd41e2 intel: Plumb the context through the decode callchain.
We still deref the context at the start of every call, but that will
change next.
2012-01-27 13:21:19 -08:00
Eric Anholt a756fa384f intel: Drop the code for counting parsing failures.
Nothing was consuming it.  If something wants this in the future,
would be done using the decode context anyway.
2012-01-27 13:21:19 -08:00
Eric Anholt 8fb66a7ded intel: Track the current packet location in the decode context.
This is the start of plumbing the context through the decode
callchain instead of the current 4 arguments.
2012-01-27 13:21:19 -08:00
Eric Anholt b5cb7f88de intel: Add a regression test for 2D decode, which I'm about to refactor. 2012-01-27 13:21:19 -08:00
Eric Anholt 683855f655 intel: Add regression tests for batch decode.
The .batch was generated using the dump-a-batch branch of

git://people.freedesktop.org/~anholt/mesa

using glxgears on gen7 hardware, using INTEL_DEVID_OVERRIDE for
non-gen7 (this means that offsets in the buffers for non-gen7 are 0!).
The .ref was generated by:

./test_decode tests/gen7-3d.batch -dump.

The .sh exists because you can't supply arguments to tests using the
simple automake tests driver.  Something reasonable could be done
using automake's parallel-tests driver (in fact, a previous version of
the patch did that), but I was concerned that:

1) The parallel-tests driver is documented to be unstable -- they may
   change interfaces on us later.
2) The parallel-tests driver hides the output of tests in .log files
   scattered all over the tree, which was ugly and more painful to
   work with.

v2: Actually add the batch files, add a .gitignore for the *-new.txt
    files added after failures, and fix failure mode for undetected
    chipset name.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)
2012-01-04 14:49:44 -08:00
Eric Anholt ccbc40340b intel: Add a regression test program for intel_decode.c.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-01-04 14:49:44 -08:00
Eric Anholt ea33a231d5 intel: Add an interface for setting the output file for decode.
Consumers often want to choose stdout vs stderr, and for testing I
want to output to an open_memstream file.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-01-04 14:49:44 -08:00
Johannes Obermayr a9dd34a7ee intel/intel_decode.c: Remove #include "intel_decode.h".
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2011-12-30 21:07:55 -08:00
Eric Anholt 4149faf337 intel: Disable unused decode_logic_op().
It was producing an unused code warning.  I'm tempted to just remove
it, since it's unused, but I *might* use it soon.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:58 -08:00
Eric Anholt 88cffcc899 intel: Turn on normal warnings for intel_decode.c build.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:56 -08:00
Eric Anholt 7b48318806 intel: Remove c99ish variable declarations.
I'd rather be able to use c99 variable declarations (there's a lot of
awful code layout due to being c90ish), but I'll leave that for later.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:50 -08:00
Eric Anholt 0c46f020c8 intel: Fix printf format warnings for intel_decode.
There was plenty of dropped useful data, and some horribly
mis-formatted data.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:47 -08:00
Eric Anholt 39a06acfbd intel: Add printflike warnings for instr_out.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:44 -08:00
Eric Anholt 1db55a80a9 intel: Fix a ton of signed vs unsigned and const char *warnings
We've got a different (better) set of warning flags in place in this
tree.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:42 -08:00
Eric Anholt 07768babb8 intel: Fix Wsigned-compare warnings (soon to be enabled).
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:39 -08:00
Eric Anholt 71066abe1e intel: Get intel_decode.c minimally building.
My plan is to use this drm_intel_dump_batchbuffer() interface for the
current GPU tools, and the current Mesa batch dumping usage, while
eventually building more interesting interfaces for other uses.

Warnings are currently suppressed by using a helper lib with CFLAGS
set manually, because the code is totally not ready for libdrm's warnings
setup.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:36 -08:00
Eric Anholt bbdda928d3 intel: Minor style tweaks after Lindent.
Some comments weren't wrapped, and for some reason uint32_t *data got
an extra space (while other instances of "type *identifier" didn't),
and the indentation of the opcode-list structs got trashed.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:33 -08:00
Eric Anholt 193fa138d7 intel: Reformat intel_decode.c from intel-gpu-tools using Lindent.
We generally go for kernel style in this tree, and this 4-space indent
stuff was bothering me.  The new results have some ugly bits, but
they're in places where we desperately want to be using helper
functions anyway.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:31 -08:00
Eric Anholt 1d318e2a79 intel: intel: Add IS_GEN[567] macros.
These will be used by intel_decode.c, and were taken from intel-gpu-tools.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:29 -08:00
Eric Anholt 078bc5b6ee intel: Make intel_chipset handle devid directly.
This will make these macros reusable from intel_decode.c, which
doesn't have a bufmgr_gem context, without faking the struct.  We
should generally only be using these macros from bufmgr_gem context
setup anyway.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:43:27 -08:00
Eric Anholt 8c4a2c8848 intel: Import intel_decode.c from intel-gpu-tools.
This is from commit dd9a5b4f7f.
We've been sharing this file between that repo and Mesa, and it's time
to build a real interface using it.  I'm also hoping to apply some of
its packet-walking logic for AUB dumping and batch validation
purposes.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29 16:42:57 -08:00
Chris Wilson 0ab2251b70 intel: Reset vma list upon purge
During free we unconditionally delete the bo from the vma cache. This
relies on the its list member being kept in a sane state. This fails
after the object is purged, as the purge operation performs a pure
deletion and doesn't reset the list member, leaving a pair of dangling
pointers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-14 08:23:02 +00:00
Chris Wilson 015286f03e intel: Remove the fresh assertions used to debug the vma cacheing
Hopefully all the bugs in the callers have been found, so time to
handle the failures "gracefully" again.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-13 10:59:13 +00:00
Chris Wilson c5f0ed1d29 intel: Update map-count for an early error return during mapping
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-13 10:41:33 +00:00
Chris Wilson dd9a5b4f7f intel: Evict cached VMA in order to make room for new mappings
As the max number of VMA mappings is a hard per-process limit, we need
to include the number of currently active mappings when evicting in
order to make room for a new mmap.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-06 21:45:55 +00:00
Chris Wilson e4b60f2960 intel: Add an interface to limit vma caching
There is a per-process limit on the number of vma that the process can
keep open, so we cannot keep an unlimited cache of unused vma's (besides
keeping track of all those vma in the kernel adds considerable overhead).
However, in order to work around inefficiencies in the kernel it is
beneficial to reuse the vma, so keep a MRU cache of vma.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-05 22:22:10 +00:00
Chris Wilson 5c5332bbc3 intel: Clean up mmaps on freeing the buffer
As a precautionary measure munmap on buffer free so that we never leak
the vma. Also include a warning during debugging.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-05 10:43:13 +00:00
Chris Wilson c549a777c1 intel: Unmap buffers during drm_intel_gem_bo_unmap
We cannot afford to cache the vma per open bo as this may exhaust the
per-process limits.

References: https://bugs.freedesktop.org/show_bug.cgi?id=43075
References: https://bugs.freedesktop.org/show_bug.cgi?id=40066
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-05 10:25:53 +00:00
Daniel Vetter 36cff1cbb8 intel: limit aperture space to mappable area on gen3
Otherwise we blow up on heavy tiled blitter loads (with giant
pixmaps).

Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-04 13:25:17 +01:00
Eric Anholt d0ae6837d1 intel: Share the implementation of BO unmap between CPU and GTT mappings.
Before this, consumers of the libdrm API that might map a buffer
either way had to track which way was chosen at map time to call the
appropriate unmap.  This relaxes that requirement by making
drm_intel_bo_unmap() always appropriate.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-10-29 12:04:09 -07:00
Eric Anholt 4cb01eeccf intel: Don't call the SW_FINISH ioctl unless a CPU-mapped write was done.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-10-29 12:03:54 -07:00
Eric Anholt 77dc16f33d intel: Remove stale comment.
This used to be next to some map refcounting code, but that is long dead.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-10-29 12:03:34 -07:00
Eric Anholt 515cea6ac6 intel: Add an interface for removing relocs after they're added.
This lets us replace the current inner drawing loop of mesa:

for each prim {
	compute bo list
	if (check_aperture_space(bo list)) {
		batch_flush()
		compute bo list
		if (check_aperture_space(bo list)) {
			whine_about_batch_size()
			fall back;
		}
	}
	upload state to BOs
}

with this inner loop:

for each prim {
 retry:
	upload state to BOs
	if (check_aperture_space(batch)) {
		if (!retried) {
			reset_to_last_prim()
			batch_flush()
		} else {
			if (batch_flush())
				whine_about_batch_size()
			goto retry;
		}
	}
}

This avoids having to implement code to walk over certain sets of GL
state twice (the "compute bo list" step).  While it's not a
performance improvement, it's a significant win in code complexity:
about -200 lines, and one place to make mistakes related to aperture
space instead of N places to forget some BO we should have included.

Note how if we do a reset in the new loop , we immediately flush.  We
don't need to check aperture space -- the kernel will tell us if we
actually ran out of aperture or not.  And if we did run out of
aperture, it's because either the single prim was too big, or because
check_aperture was wrong at the point of setting up the last
primitive.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-10-28 12:53:59 -07:00
Eric Anholt 2c2bdb36c5 intel: Use stdbool.h for dealing with boolean values.
A few of the bitfield-based booleans are left in place.  Changing them
to "bool" results in the same code size, so I'm erring on the side of
not changing things.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-10-28 12:53:18 -07:00
Daniel Vetter 194aa1bee6 drm/i915: y tiling on i915G/i915GM is different
Luckily the kernel has become extremely paranoid about such matters.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-09-22 22:20:53 +02:00
Daniel Vetter 630dd26fb4 drm/intel: don't clobber bufmgr->pci_device
Otherwise it's pretty hard to differentiate the different chipset
variants.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-09-22 22:20:09 +02:00
Ben Widawsky 2acaf160df intel: shared header for shader debugging
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
2011-08-01 14:44:58 -07:00
Yuanhan Liu ce317a6d09 intel: fix the wrong method check for bo_get_subdata
It's going to call bo_get_subdata method, but not bo_subdata

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-07-20 10:46:45 -07:00
Chris Wilson 9d77603d8b intel: Add interface to query aperture sizes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-06-04 13:01:11 +01:00
Chris Wilson f395b0a25c intel: Also handle mrb_exec fallback with ring == I915_EXEC_RENDER
Reported-by: Oliver McFadden <oliver.mcfadden@nokia.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 08:59:39 +01:00
Daniel Vetter 06ebbf7c2c Cleanup gen2 tiling confusion
A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-03-26 15:04:04 +01:00
Daniel Vetter e6018c25ca intel: Fixup for the fix for relaxed tiling on gen2
This is Fail.

First patch to libdrm, and I've borked it up.

Noticed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-02-22 19:11:33 +01:00
Daniel Vetter 9a71ed93f4 intel: fix relaxed tiling on gen2
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-02-22 18:53:56 +01:00
Chris Wilson 36d4939343 intel: Remember named bo
... and if asked to open a bo by the same global name, return a fresh
reference to the previously allocated buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-14 10:18:39 +00:00
Chris Wilson 53581b6210 intel: Set the public handle after opening by name
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-14 10:15:31 +00:00
Chris Wilson 550fe2ca3b intel: compile fix for previous commit after rebasing
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-12 15:06:25 +00:00
Chris Wilson 6717b7579f intel: Fallback to old exec if no mrb_exec is available
Reported-by: Torsten Hilbrich <torsten.hilbrich@secunet.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33016
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-12 11:00:13 +00:00
Chris Wilson 0184bb1c6d intel: Export CONSTANT_BUFFER addressing mode
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-19 13:01:15 +00:00
Chris Wilson 537703fd48 intel: Reorder need_fence vs fenced_command to avoid fences on gen4
gen4+ hardware doesn't use fences for GPU access and the older kernel
doesn't expect userspace to make such a mistake. So don't.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32190
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 20:34:22 +00:00
Chris Wilson af3d282afb intel: If the command is fenced inform the kernel
... but only account for a fenced used if the object is tiled.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 10:51:49 +00:00
Chris Wilson 1443bea488 intel: Add a forward declaration of struct drm_clip_rect
... so that intel_bufmgr.h can be compiled standalone.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25 16:59:20 +00:00
Chris Wilson 51b895041c intel: Compute in-aperture size for relaxed fenced objects
For relaxed fencing the object may only consume the small set of active
pages, but still requires a fence region once bound into the aperture.
This is the size we need to use when computing the maximum possible
aperture space that could be used by a single batchbuffer and so avoid
hitting ENOSPC.

Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 09:54:47 +00:00
Eric Anholt 877b2ce15b intel: Fix drm_intel_gem_bo_wait_rendering to wait for read-only usage too.
Both the consumers of this API (sync objects and client throttling)
were expecting this behavior.  The kernel used to actually behave the
desired (but incorrect) way for us anyway, but that got fixed a while
back.
2010-11-09 13:57:19 -08:00
Albert Damen 49447a9b95 intel: initialize bufmgr.bo_mrb_exec unconditionally
If bufmgr.bo_mrb_exec is not set, drm_intel_bo_mrb_exec returns ENODEV
even though drm_intel_gem_bo_mrb_exec2 will work fine for the RENDER ring.
Fixes xf86-video-intel after commit 'add BLT ring support' (5bed685f76)
with kernels without BSD or BLT ring support (2.6.34 and before).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31443
Signed-off-by: Albert Damen <albrt@gmx.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-07 14:59:55 +00:00
Eric Anholt a52e61b5c8 intel: Drop silly asserts on mappings present at unmap time.
The intent of these was to catch mismatched map/unmap.  What it
actually did was check whether there was ever a mapping of that type
(including in a previous life of the buffer through the userland BO
cache), not whether they were mismatched.  We don't even actually want
to catch mismatched map/unmap, unless we also do refcounting, since at
one point Mesa would do map/map/use/unmap/unmap.  Just remove this
code instead.
2010-11-02 11:32:32 -07:00
Eric Anholt 4abb65f95c intel: Remove gratuitous assert on bo_reference.
This couldn't be triggered except by overflow, since there's an assert
in unreference to catch the usual failure of over-unreferencing.
2010-11-02 11:19:21 -07:00
Eric Anholt f45305c1aa intel: Shove the fake bufmgr subdata implementation into the fake bufmgr. 2010-11-01 06:54:58 -07:00
Eric Anholt 6560b4766c intel: Remove stale comment. 2010-11-01 06:50:04 -07:00
Chris Wilson 362457715f intel: enable relaxed fence allocation for i915
The kernel has always allowed userspace to underallocate objects
supplied for fencing. However, the kernel only allocated the object size
for the fence in the GTT and so caused tiling corruption. More recently
the kernel does allocate the full fence region in the GTT for an
under-sized object and so advertises that clients may finally make use
of this feature. The biggest benefit is for texture-heavy GL games on
i945 such as World of Padman which go from needing over 1GiB of RAM to
play to fitting in the GTT!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29 10:49:54 +01:00
Chris Wilson 057fab3382 intel: Prepare for BLT ring split.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-26 11:41:40 +01:00
Chris Wilson 96214860bb intel: Downgrade error warnings to debug
As the higher layers check the error return from libdrm-intel and
are supposed to handle the error (and print their own warning in
extremis) the voluminous output on stderr is just noise and a hazard in
its own right.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-01 16:42:38 +01:00
Chris Wilson 6299722c47 intel: Replace open-coded drmIoctl with calls to drmIoctl()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-25 21:38:31 +01:00
Eric Anholt 23287f05cf Avoid use of c++ reserved keyword "virtual" when using a C++ compiler.
Avoids requiring nasty hacks around libdrm headers in the new C++
parts of Mesa drivers.
2010-08-26 15:45:12 -07:00
Chris Wilson c3ddfea1a6 intel: Suppress the error return from setting domains after mapping.
If the mapping succeeds we have a valid pointer. If setting the domain
failures we may incur cache corruption. However the usual failure mode
is because of a hung GPU, in which case it is preferable to ignore the
minor error from setting the domain and continue on oblivious. If
these errors persist, we should rate limit the warning [or even just
remove it].

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-29 20:16:56 +01:00
Chris Wilson 726210f87d intel: Limit tiled pitches to 8192 on pre-i965.
Fixes:

  Bug 28515 - Failed to allocate framebuffer when exceed 2048 width
  https://bugs.freedesktop.org/show_bug.cgi?id=28515

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-24 11:38:00 +01:00
Chris Wilson 6ea2bda5f5 intel: Only adjust the local stride used for SET_TILING in tiled alloc
Mesa uses the returned pitch from alloc_tiled, so make sure that we set
it correctly before modifying the stride used for the SET_TILING call.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-22 13:03:52 +01:00
Chris Wilson aba3502190 intel: Restore SET_TILING for non-flinked bo.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-22 13:00:22 +01:00
Chris Wilson c7bbaca6a3 intel: '===' != '=='
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-22 11:15:56 +01:00
Chris Wilson cd34cbeb9f intel: Sanitise strides for linear buffers and SET_TILING
Ensure that the user doesn't attempt to specify a stride to use with a
linear buffer by forcing such to be zero.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-22 11:09:12 +01:00
Chris Wilson 13e8270504 intel: Print out debugging message following ENOSPC
execbuffer() returns ENOSPC if it cannot fit the batch buffer into the
aperture which is the error we want to diagnose here.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-21 22:37:18 +01:00
Chris Wilson f16b4164d6 intel: Scan the cache for old bo once every second.
Rearrange the cache cleanup so that we always scan following a final
unreference, and guard against multiple scans in a single second.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-21 22:37:18 +01:00
Chris Wilson 5eec286838 intel: Force stride to be 0 for I915_TILING_NONE.
When allocating a tiled buffer, if we remove the desired tiling mode due
to it being beyond hardware limits, also remove the stride. This ensures
that we only ever use stride 0 with I915_TILING_NONE.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-21 22:37:18 +01:00
Chris Wilson 1db22ff741 intel: Defer tiling change to allocation.
As we now expose a method to allocate tiled buffers, it makes more sense
to defer the SET_TILING until required. Besides the slim chance that it
will be a no-op, by delaying the change we are less likely to stall on
waiting for a bound buffer to release a fence register.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-21 22:37:18 +01:00
Chris Wilson 056aa9be04 intel: Track tiling stride
We need to inform the kernel if the tiling stride changes and not only
for changes of the tiling mode.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-21 14:25:39 +01:00
Eric Anholt 4f7704aea7 intel: Fix several other paths for buffers pointing at themselves. 2010-06-10 09:02:14 -07:00
Eric Anholt 0ec768e67a intel: Add more intermediate sizes of cache buckets between powers of 2.
We had two cases recently where the rounding to powers of two hurt
badly: 4:2:0 YUV HD video frames would round up from 2.2MB to 4MB, and
Urban Terror was hitting aperture size limitations.  For UT, this is
because mipmap trees for power of two texture sizes will land right in
the middle between two cache buckets.

By giving a few more sizes between powers of two, Urban Terror on my
945 ends up consuming 207MB of GEM objects instead of 272MB, and HD
video decode on Ironlake goes from 99MB to 75MB.

cairo-perf-diff of the benchmarks for gl and xlib shows a 1.09x and
1.06x speedup and a 1.07x, 1.08x, and 1.11x slowdown.  From this, I
think this patch was really a no-op in terms of performance for these
CPU-bound workloads.
2010-06-10 08:56:56 -07:00
Chris Wilson e65caeba9e intel: Convert to untiled pitches if surface is too large for tiling.
If the pitch is too large for the hardware to tile, recompute the
required surface size based on the untiled pitch and alignments. For the
older hardware, which has smaller limits and greater restrictions, this
may be a considerable saving in allocation size.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-09 10:18:31 +01:00
Eric Anholt f179137f8f Allow a buffer to point at itself and still get relocs.
I'm using this in experiments with the i965 Mesa driver.
2010-06-07 17:29:57 -07:00
Zou Nan hai 66375fd6e8 intel: Add support for kernel multi-ringbuffer API.
This introduces a new API to exec on BSD ring buffer, for H.264 VLD
decoding.

Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2010-06-06 15:50:38 -07:00
Eric Anholt 58e54f62c9 intel_bufmgr_fake: fix compile warning. 2010-05-26 12:10:39 -07:00
Chris Wilson fcf3e616ee intel: Don't change tiling mode unless the kernel reports success.
Fixes:

  Bug 26686 - Some textures are distorted with libdrm 2.4.18 in GTAVC&GTA3
  http://bugs.freedesktop.org/show_bug.cgi?id=26686

This bug continues to haunt me. The kernel SET_TILING ioctl is
inconsistent in its return values when reporting an error. If one of its
sanity checks fail, then the input values are left unchanged. If the
kernel later fails to change the tiling mode, then the input values are
modified to match the current tiling on the object. In short, userspace
cannot trust the return values upon error and so we must assume that
upon error our current tiling mode matches reality and not update.
2010-05-24 18:38:29 +01:00
Chris Wilson a3305b076c Revert "intel: We don't need to take the bufmgr lock whilst mapping."
This reverts commit 7ca558494d.

This was pushed ahead of an essential review of bo level locking in
mesa, without which we cannot know whether removing this lock is safe.
2010-05-13 08:25:56 +01:00
Chris Wilson 07e7589d86 intel: query whether a buffer is reusable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-05-11 08:54:06 +01:00