Commit Graph

51 Commits (5f427e9aaed76ec827b9523b4022205f5bd09a4a)

Author SHA1 Message Date
Maarten Maathuis bc32d1798a NV50: some i2c cleanup 2008-07-01 15:14:30 +02:00
Maarten Maathuis 473a1997ac NV50: Initial import of kernel modesetting. 2008-06-22 16:29:00 +02:00
Maarten Maathuis 1692d30cea nv50: primitive i2c interrupt handler 2008-04-05 21:02:00 +02:00
Maarten Maathuis 3fc444a5e8 nv50: primitive display interrupt handler. 2008-04-03 01:13:31 +02:00
Ben Skeggs 15cbde683f nv40: actually init all tile regs. 2008-02-16 04:47:02 +11:00
Maarten Maathuis 733e07663e nouveau: NV40 can/should now be able to run after the blob.
- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.
2008-02-02 12:46:47 +01:00
Stuart Bennett 71adbfc874 [PATCH] nouveau: reset AGP on init for < nv40
This is necessary for AGP to work after running bios init scripts on nv3x, and
is seen in mmio traces of all cards (nv04-nv4x)

I'm not making the equivalent change to nv40_mc.c, as early cards (6200, 6800gt)
use the 0x000018XX PBUS and later cards use the 0x000880XX PBUS and I don't know
the effects of using the wrong one
2008-01-04 05:08:15 +01:00
Ben Skeggs 2d7eb4434f nouveau: Also wait until CACHE1 gets emptied. 2007-11-14 05:36:20 +11:00
Ben Skeggs 7246a33dd1 nouveau: store user control reg offsets in channel struct 2007-11-14 04:09:53 +11:00
Ben Skeggs d0904f0f2b nouveau: funcs to determine active channel on PFIFO. 2007-11-14 03:27:37 +11:00
Dave Airlie 7f6bf84c23 drm: remove lots of spurious whitespace.
Kernel "cleanfile" script run.
2007-11-05 12:42:22 +10:00
Matthieu Castet bf126f4925 nouveau : nv10 and nv04 PGRAPH_NSTATUS are different 2007-10-10 21:11:43 +02:00
Stephane Marchesin 9b294bbe0e nouveau: try to fix big endian. 2007-10-10 01:12:20 +02:00
Matthieu Castet 9cd6ece307 nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idle
Also clean PGRAPH_CHANNEL macros
2007-09-30 23:09:30 +02:00
Patrice Mandin 0bd8752a0c nouveau: nv10: add combiner registers 2007-09-10 18:53:48 +02:00
Matthieu Castet a331d2e352 nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition
- fix offset for nv04
- use it in nv10 graph ctx switch for getting next channel
- dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-26 20:48:32 +02:00
Ben Skeggs a654c0341a nouveau/nv40: Dump extra info on ucode state if ctx switch fails. 2007-08-22 13:19:21 +10:00
Ben Skeggs a46104674f nouveau/nv50: demagic instmem setup. 2007-08-10 14:22:50 +10:00
Pekka Paalanen 0c77f5abea nouveau: Add bitfield names for NSOURCE and NSTATUS.
Name strings and pretty-printing in nouveau_graph_dump_trap_info().
2007-07-18 14:00:04 +03:00
Pekka Paalanen 14ecf8d6c2 nouveau: Replace 0x00400104 and 0x00400108 with names.
NV03_PGRAPH_NSTATUS and NV03_PGRAPH_NSOURCE.
The prefix NV03 is chosen because nv10reg.h had no versioned prefix,
and the code using these registers does not check card_type.
2007-07-18 13:52:39 +03:00
Arthur Huillet 694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs 38617b6a26 nouveau: name some regs 2007-06-28 03:26:44 +10:00
Ben Skeggs 05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00
Ben Skeggs f2e64d5276 nouveau: NV4X PFIFO engtab functions 2007-06-24 18:56:01 +10:00
Ben Skeggs 78034c06df nouveau: make a note about a bit that breaks some cards 2007-04-06 03:27:55 +10:00
Ben Skeggs 674cefd4fe nouveau: move card initialisation into the drm
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.

It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
Ben Skeggs 1b3a6d4775 nouveau: remove a hack that's not needed since the last interface change. 2007-03-07 21:17:45 +11:00
Ben Skeggs 72caa48c82 nouveau: intrusive drm interface changes
graphics objects:
	- No longer takes flags/dmaobj parameters, requires some major changes
	  to the ddx to setup the object through the FIFO.  This change is
	  likely to cause breakages on some cards (tested on NV05,NV28,NV35,
	  NV40 and NV4E).
dma objects:
	- now takes a "class" parameter, not really used yet but we may need
	  it at some point.
	- parameters are checked, so clients can't randomly create DMA objects
	  pointing at whatever they feel like.
misc:
	- Added FB_SIZE/AGP_SIZE getparams
	- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
	- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
	  NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Stephane Marchesin 17985f07d6 nouveau: more work on the nv04 context switch code. 2007-02-06 01:17:32 +01:00
Stephane Marchesin 7ab9e7f36f nouveau: cleanup the nv04 pgraph save/restore mechanism. 2007-02-03 05:56:42 +01:00
Stephane Marchesin 5a072f32c8 nouveau: rename registers to their proper names. 2007-02-03 04:57:06 +01:00
Stephane Marchesin e64dbef911 nouveau: add NV04 registers required for PGRAPH context switching. 2007-02-03 04:23:09 +01:00
Patrice Mandin e7ba15a003 nouveau: add extra pgraph registers 2007-01-26 19:24:34 +01:00
Matthieu Castet f04347f371 nouveau: nv20 graph ctx switch.
Untested...
2007-01-13 23:19:41 +01:00
Matthieu Castet 4ae64a1b58 nouveau: add and indent pgraph regs 2007-01-13 21:44:50 +01:00
Stephane Marchesin 1967aa82cf nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value. 2007-01-13 12:32:50 +01:00
Jeremy Kolb 4297a83b48 nouveau: get nv30 context switching to work.
* Pulled in some registers from nv10reg.h.  Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation.  Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
Ben Skeggs dbb0d979cc nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load. 2007-01-06 17:50:00 +11:00
Stephane Marchesin f80659bc29 Cleanup the nv04 fifo code a bit. 2007-01-05 19:37:06 +01:00
Matthieu Castet f48a7685bd For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
Ben Skeggs 2fd812f8ef Completely untested NV10/20/30 FIFO context switching changes. 2006-11-14 09:00:31 +11:00
Ben Skeggs 7002082944 Restructure initialisation a bit.
- Do important card init in firstopen
 - Give each channel it's own cmdbuf dma object
 - Move RAMHT config state to the same place as RAMRO/RAMFC
 - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
Dave Airlie 2dd3c039fd fixup fifo size so it is page aligned 2006-11-06 11:42:15 +11:00
Ben Skeggs b5cf0d635c Remove hack which delays activation of a additional channel. The previously active channel's state is saved to RAMFC before PFIFO gets clobbered. 2006-10-18 02:37:19 +11:00
Ben Skeggs 55de3f763f Useful output on a FIFO error interrupt. 2006-10-17 23:44:05 +11:00
Ben Skeggs 1943f39d8c Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup code a bit. 2006-10-17 06:37:40 +11:00
Ben Skeggs 95486bbde0 Some info on NV40's RAMFC 2006-10-17 06:12:18 +11:00
Stephane Marchesin 7ef44b2b8d Still more work on the context switching code. 2006-10-12 17:31:49 +02:00
Stephane Marchesin dd473411f8 Context switching work.
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
2006-10-11 00:28:15 +02:00