When running ras inject test, it's needed to be aligned
with kernel's ras enablement.
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Both UMC and GFX ras single_correctable
inject tests are added.
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Json package dependence is removed from amdgpu_test,
so this json configuration file is not needed any more.
Suggested-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Except CUnit library, no additional external
library should be needed when compiling amdgpu_test.
This will keep this binary self containing.
Suggested-by: Christian König <christian.koenig@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
On Solaris, sys/sysmacros.h has long-deprecated copies of major() & minor()
but not makedev().
sys/mkdev.h has all three and is the preferred choice.
Let's make sure we check for all 3 major(), minor() and makedev().
Fixes build failure with error:
../xf86drm.c: In function ‘drmOpenMinor’:
../xf86drm.c:454:30: error: implicit declaration of function ‘makedev’ [-Werror=implicit-function-declaration]
454 | return drmOpenDevice(makedev(DRM_MAJOR, minor), minor, type);
| ^~~~~~~
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Tested-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Add the new CML PCI IDS.
Align with kernel commit:
bfc4c359b2822 ("drm/i915/cml: Add Missing PCI IDs")
This is in sync with kernel header as of:
0747590267e7 ("drm-tip: 2019y-08m-30d-18h-03m-18s UTC integration manifest")
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Both umc single_correctable and multi_uncorrectable
inject types are added.
Signed-off-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ras inject test framework is invalid with original codes,
so refine it to make it work on top of kernel ras inject
feature enablement.
Signed-off-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This configuration file will be picked up when
running gfx ras inject tests by amdgpu_test tool.
For the time being, only add those tests that are
successfully trafficked. In addition, this file
can also be modified by user to add or delete ras
inject unit tests for different IP blocks/subblocks.
Signed-off-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
for better clarification
v2: accordingly change dispatch_test caller in gpu_reset test
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ASIC hang randomly.
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add the PCI ID import for EHL.
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Straight copy from the kernel file, aligned with drm-intel-next-queued
commit cb823ed9915b ("drm/i915/gt: Use intel_gt as the primary object
for handling resets")
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
1. perform gpu reset
2. perform dispatch test to verify gpu reset to a good state
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
1. skip test if there's no desired ring
2. clear shader buffer
3. update command buffer for gfx9
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Adapted from a local patch carried by DragonFlyBSD:
bc056f88f7/graphics/libdrm/files/patch-xf86drm.h
Patch is sadly uncredited (a bot authored the commit), so I can't credit
the author here either.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
drm render nodes have the same major as drm primary devices but offset
the minor by a base of 128.
I expected the name of the device to have numbering starting at 0 when
these non-linux codepaths were added (before OpenBSD had render nodes).
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Unlike Linux the OpenBSD primary "drm" device name is substring of the
"drmR" render node device name and strncmp() tests resulted in render
nodes being flagged as primary nodes.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Make it actually clear the LUT.
Reported-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Simplifies its callers.
dev->bo_table_mutex is now always held when amdgpu_bo_create is called
(this was already the case in amdgpu_bo_import).
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
And propagate drmIoctl's return value.
This allows replacing all remaining open-coded DRM_IOCTL_GEM_CLOSE
ioctl calls with amdgpu_close_kms_handle calls.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
The following situation can happen in a multithreaded OpenGL application.
A BO is submitted from etna_cmd_stream #1 with flags set for read.
A BO is submitted from etna_cmd_stream #2 with flags set for write.
This triggers a flush on stream #1 and clears the BO's current_stream
pointer. If at this point, stream #2 attempts to queue BO again, which
does happen, the BO will be added to the submit list twice. The Linux
kernel driver correctly detects this and warns about it with "BO at
index %u already on submit list" kernel message.
However, when cleaning the BO cache in etna_bo_cache_free(), the BO
which was submitted twice will also be free()d twice, this triggering
a glibc double free detector.
The fix is easy, even if the BO does not have current_stream set,
iterate over current streams' list of BOs before adding the BO to it
and verify that the BO is not yet there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Avoids compiler warning:
../../amdgpu/amdgpu_cs.c: In function 'amdgpu_cs_ctx_override_priority':
../../amdgpu/amdgpu_cs.c:155:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
union drm_amdgpu_sched args;
^~~~~
Reviewed-by: Christian König <christian.koenig@amd.com>
There is no implementation and also no users, so there is no point
in keeping it in the API.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Instead of hacking the binary every time, we can now specify directly.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This includes logic to configure the LUT accordingly.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
As new features are added and others are declared to be legacy, it's
nice to be able to implement fallbacks. As such, create a
property-setting variant that does not generate errors which can very
well be entirely expected.
Will be used for gamma control in a future change.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This change adds support for all current patterns.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
The idea is to have a horizontal pattern split into two with the top and
bottom halves having different precision. This allows one to see whether
10bpc support is working properly or not, as there are many pieces to
the puzzle beyond the basic format support (gamma ramps, bpc encodings,
etc).
This is really only useful on 10bpc formats, but we also add support for
8bpc formats to ease testing. In the future, this could be applied to
16bpc formats as well.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
We need to shift the values up, otherwise we'd end up with a negative
shift. This works for up-to 16-bit components, which is fine for now.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This also adds a helper to generate a color LUT, which has to be used in
conjunction with the C8 indexed format.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
With different register offsets from VCN1.0
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10
Reviewed-by: Tim Writer <Tim.Writer@amd.com>
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
pa_sc_tile_steering_override is a new member introduced for gfx10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Feature is controlled by DRM_CAP_SYNCOBJ_TIMELINE drm capability.
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
a) delta: only DRM_CAP_SYNCOBJ_TIMELINE
b) Generated using make headers_install.
c) Generated from origin/drm-misc-next commit 982c0500fd1a8012c31d3c9dd8de285129904656"
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Suggested-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Niclas Zeising
Le Ma
Guchun Chen
Eric Engestrom
Anusha Srivatsa
Flora Cui
Rodrigo Vivi
Lucas De Marchi
Jonathan Gray
Ilia Mirkin
Marek Olšák
Michel Dänzer
Marek Vasut
Lucas Stach
Leo Liu
Tao Zhou
Hawking Zhang
Huang Rui
Chunming Zhou