Commit Graph

5444 Commits (9588e66dbd695dce24e0aba54eaf94f573ab5363)

Author SHA1 Message Date
Chris Wilson 8cf3475eb5 intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-10-07 10:09:38 +01:00
Chris Wilson 75830a0d2c intel: Fix "properly test for HAS_LLC"
commit 92fd0ce4f6
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Aug 31 11:16:53 2012 +0200

    intel: properly test for HAS_LLC

missed slightly and in effect had no effect on the outcome of checking
whether the kernel/chipset supported LLC.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-10-07 10:09:38 +01:00
Marek Olšák 1aebfdc112 radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI
This allows texturing with depth-stencil buffers directly without the copy
to CB. The separate miptree description for stencil is added, because
the stencil mipmap offsets are not really depth offsets/4 (at least
for the texture units).

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06 05:45:56 +02:00
Marek Olšák 77413e77b8 radeon: don't force stencil tile split to 0
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-06 05:45:26 +02:00
Marek Olšák b3d90bbc1d radeon: don't take the stencil-specific codepath for buffers without stencil
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-03 17:52:44 +02:00
Jesse Barnes 2426a6a711 libdrm: man page infrastructure and a few sample man pages 2012-09-17 08:07:04 -07:00
Kristian Høgsberg 1b7ce582ce intel: Mark bo's exported to prime as not reusable
It's the same situation as flink and we need take the same precautions.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-09-14 22:06:14 -04:00
Jesse Barnes 9d9cb8553c intel: add support for ValleyView
Just some PCI ID stuff to enable the right features.
2012-09-13 11:50:59 -07:00
Marcin Slusarz 9c3c95fc0c libkms: link against libdrm
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
2012-09-08 00:50:22 +02:00
Michel Dänzer b925022a3e radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.
Another corner case that isn't well-explained yet.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:25:13 +02:00
Michel Dänzer 45083e6d36 radeon: Memory footprint of SI mipmap base level is padded to powers of two.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:24:44 +02:00
Michel Dänzer 8572444fd0 radeon: Fix layout of linear aligned mipmaps on SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-05 18:47:49 +02:00
Daniel Vetter 92fd0ce4f6 intel: properly test for HAS_LLC
If the kernel supports the test, we need to check the param.
Copy&pasta from the above checks that only look at the return value.
Interesting how much one can get such a simple interface wrong.

Issue created in

commit 151cdcfe68
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date:   Tue Jan 17 15:20:19 2012 -0200

    intel: query for LLC support

Patch even claims to have fixed this in v2, but is actually unchanged
from v1.

Reported-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-09-01 11:21:38 +02:00
Jakob Bornecrantz 7080bfdfd9 vmwgfx: No longer experimental
And hasn't been in a long while.

Reviewed-by: Zack Rusin <zackr@vmware.com>
Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
2012-08-24 17:17:43 +02:00
Marek Olšák ae3ac8225f configure: bump version for 2.4.39 release 2012-08-24 17:04:17 +02:00
Marek Olšák 853429b939 radeon: align r600 msaa buffers to a multiple of macrotile size * num samples
I am not sure whether this is needed, but better be safe than sorry.
2012-08-24 16:51:14 +02:00
Marek Olšák 58545722d0 radeon: fix allocation of MSAA surfaces on r600-r700
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-24 16:51:14 +02:00
Víctor Manuel Jáquez Leal f215d65137 omap: include omap_drm.h independently
omap_drm.h uses data type defined in stdint.h, but that header was
not included.

omap_drm.h includes drm.h as a local file when it is part of the
compiler c flags.

This two issues are fixed. New code can include omap_drm.h alone.

Signed-off-by: Víctor Manuel Jáquez Leal <vjaquez@igalia.com>
Signed-off-by: Rob Clark <rob@ti.com>
2012-08-23 14:21:01 -05:00
Dave Airlie 3163cfe4db radeon: add prime import/export support
this adds radeon version of the prime import/export support.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-08-14 11:04:56 +10:00
Kenneth Graunke a9412fa9de intel: Use VG_CLEAR on the context destroy ioctl as well.
Otherwise pad appears uninitialized and valgrind grumbles.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-12 20:13:50 -07:00
Tobias Klausmann 6fa2b29d22 tests/modetest: Add a forgotten return, needed for opensuse buildservice
Signed-off-by: Marek Olšák <maraeo@gmail.com>
2012-08-12 00:00:43 +02:00
Marek Olšák d1de6831b9 configure: bump version for 2.4.38 release 2012-08-11 20:06:23 +02:00
Marek Olšák 10481fec55 tests/modetest: fix distcheck 2012-08-11 20:02:03 +02:00
Eric Anholt 2607dad20b intel: Add a function for the new register read ioctl.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2012-08-10 09:48:07 -07:00
Eric Anholt 934ea3b321 intel: Import updated i915_drm.h.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2012-08-10 09:48:05 -07:00
Eric Anholt 71ebcf4ea3 Drop "-Wunsafe-loop-optimizations".
It warns about totally sensible things done in intel_decode.c.  I've
never seen this warn do anything useful, and apparently I was the one
to introduce it when I added the giant pile of warning flags back in
2008.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2012-08-10 09:48:02 -07:00
Marek Olšák 128803a107 radeon: tweak TILE_SPLIT for MSAA surfaces
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09 22:35:07 +02:00
Marek Olšák e14aedce64 radeon: force 2D tiling for MSAA surfaces
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09 22:33:00 +02:00
Marek Olšák 2337295573 radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.

v2: actually do it correctly

Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-09 16:37:20 +02:00
Marek Olšák ad66c17209 radeon: simplify ZS buffer checking on r600
Setting those flags has no effect anywhere else.

Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-09 16:37:20 +02:00
Paulo Zanoni 93fef04b1e intel: add more Haswell PCI IDs
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2012-08-08 15:38:12 -03:00
Chris Wilson 9a2b57d229 intel: Bail gracefully if we encounter an unknown Intel device
Otherwise we end up with X hitting a fail-loop as the embedded libGL
stacks asserts whilst initialising.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-08 19:24:11 +01:00
Alex Deucher 9f823ca236 radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06 10:34:59 -04:00
Alex Deucher dd944a0081 radeon: add some missing evergreen pci ids
Noticed by: Harald van Dijk <fdo@gigawatt.nl>

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=53124

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06 10:33:56 -04:00
Eric Anholt 7e3f08b463 intel: Quiet valgrind warnings in context creation. 2012-08-02 11:20:17 -07:00
Damien Lespiau c10b08d959 intel: Remove two unused variables
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-02 11:20:06 -07:00
Rob Clark ebd7904877 modetest: fix uninitialized fourcc
If color format for CRTC layer is not specified on commandline, then
c->fourcc is unintialized resulting in addfb call failing.

Signed-off-by: Rob Clark <rob@ti.com>
2012-07-23 11:35:06 -05:00
Laurent Pinchart db004badef modeset: Split buffer allocation to a separate file
As the modeset test application is often referred to as an example of
the KMS API usage, move test pattern generation and buffer allocation to
a separate file to keep it simple and clear.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:47 -05:00
Laurent Pinchart cc90ffa9b1 modetest: Make frame buffer format configurable on the command line
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:47 -05:00
Laurent Pinchart 0375222c71 modetest: Move connector and plane parsing to separate functions
This will make it easier to add additional parameters to the connector
and plane arguments.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:47 -05:00
Laurent Pinchart edcef53685 modetest: Add test pattern support for missing RGB formats
Implement tiles and SMPTE test pattern generation for the RGB565,
BGR888, RGB888, ARGB8888, BGRA8888 and BGRX8888 formats.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:47 -05:00
Laurent Pinchart 86402a2a0c modetest: Add test pattern support for missing planar YUV formats
Implement tiles and SMPTE test pattern generation for the NV12, NV21,
NV16 and NV61 formats.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:47 -05:00
Laurent Pinchart 8b6f3e32b8 modetest: Add test pattern support for missing packed YUV formats
Implement tiles and SMPTE test pattern generation for the UYVY, VYUY and
YVYU formats.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:47 -05:00
Laurent Pinchart a94ee62429 modetest: Add SMPTE test pattern
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:46 -05:00
Laurent Pinchart 3fdc1777ee modetest: Unify buffer allocation
Merge the create_test_buffer() and create_grey_buffer() functions into a
single buffer allocation function that takes the pixel format and fill
pattern as parameters.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2012-07-20 10:30:46 -05:00
Rob Clark faf26b689d intel: fix build error
CCLD   test_decode
./.libs/libdrm_intel.so: undefined reference to `drmPrimeHandleToFD'
./.libs/libdrm_intel.so: undefined reference to `drmPrimeFDToHandle'
collect2: ld returned 1 exit status

From Adam Jackson's explaination:

  most distros have changed it so ld defaults to --no-copy-dt-needed-entries,
  so if you use something from libdrm you can't just assume libdrm_intel
  will bring it in for you, you have to be explicit

Signed-off-by: Rob Clark <rob@ti.com>
2012-07-20 10:28:46 -05:00
Dave Airlie ff65de9666 intel: add prime interface for getting/setting a prime bo. (v4)
This adds interfaces for the X driver to use to create a
prime handle from a buffer, and create a bo from a handle.

v2: use Chris's suggested naming (well from at least for consistency)
v3: git commit --amend fail
v4: fix as per Chris's suggestions, group assignments, add get tiling

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-20 08:53:03 +10:00
Dave Airlie 13c06cde4e libdrm/nouveau: add prime handle->bo and bo->handle support.
This adds prime support to nouveau libdrm.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-19 13:05:57 +10:00
Dave Airlie cc0a14575d libdrm: add prime fd->handle and handle->fd interfaces
These are just basic ioctl wrappers around the prime ioctls,
along with the capability reporting.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-16 02:39:56 +01:00
Dave Airlie 41dfb20cdc libdrm: add missing caps from kernel to drm.h
This just moves over some missing caps from the kernel.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-16 02:39:12 +01:00