Commit Graph

300 Commits (d05b9f2dde17e60996437332219b4b568f7edefa)

Author SHA1 Message Date
Grazvydas Ignotas 1924b6704a libdrm: random typo fixes
Just some trivial boring typo fixes all over the tree.
READMEs and comments only.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-11-22 13:54:31 +00:00
Michel Dänzer 911280cb4a intel: Add drm_intel_gem_context_get_id to intel-symbols-check
Fixes make check. Trivial.
2016-11-22 15:48:12 +09:00
Robert Bragg 770f6bc424 intel: Add a getter for the intel_context ctx_id
Exposing the u32 context ID makes it possible to define new drm kernel
interfaces based on the same IDs that e.g. execbuf uses to identify a
gem context, that aren't themselves abstracted by libdrm but need to be
used by libdrm/drm_intel_context based clients such as (parts of) i-g-t
or Mesa.

For example this can be used to configure an i915-perf stream to collect
metrics for a specific context.

v2: s/drm_intel_gem_context_get_context_id/drm_intel_gem_context_get_id/

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
2016-11-21 16:33:55 +00:00
Ben Widawsky 3e81f8b7b9 intel: Add Geminilake PCI IDs
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-11-18 15:57:55 -08:00
Matt Turner 51002c0440 intel: Add uthash.h to Makefile.sources. 2016-11-14 10:40:59 -08:00
Neil Roberts 319108f947 intel: Allow some codenames in INTEL_DEVID_OVERRIDE
As well as allowing a hexadecimal PCI ID number, the
INTEL_DEVID_OVERRIDE environment variable can now contain one of a few
short codenames. The codenames are stored in a small table to map them
to a corresponding PCI ID. This makes it easier to use without having
to look up the PCI IDs manually.

The PCI IDs used are the same as those chosen for the -p option of
run.c in shader-db but SKL has been added as well.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-11-14 10:40:58 -08:00
Chris Wilson fe4579e263 intel: Look prime handle up in handle hash table
A slightly confused copy'n'paste from the open path where we pass in
handle but use it as a global name, in the prime handle-from-fd pass we
pass in handle and do mean handle!

References: https://bugs.freedesktop.org/show_bug.cgi?id=98416
Fixes: 2f23bf1b7b89 ("intel: Migrate handle/name lookups from linear lists...")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-24 21:19:52 +01:00
Michel Dänzer ec39fe07e7 intel: Add new symbols to intel-symbol-check
Fixes make check.

Trivial.
2016-10-24 11:14:36 +09:00
Chris Wilson 9e24d0c54b intel: Migrate handle/name lookups from linear lists to hashtables
Walking a linear list to find a matching PRIME handle or flinked name
does not scale and becomes a major burden with just a few objects.
That said, the fixed size hash is not much better, it just buckets the
look into a few separate chains rather than one long one.

References: https://bugs.freedesktop.org/show_bug.cgi?id=94631
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-22 09:32:54 +01:00
Chris Wilson 455e9b4917 intel: Export raw GEM mmap interfaces
Export a set of interfaces to allow the caller to have precise control
over mapping the buffer - but still provide caching of the mmaps between
callers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-22 09:32:54 +01:00
Michel Dänzer 2d00869599 intel: Add new symbols to intel-symbol-check
Fixes make check.

Trivial.
2016-09-08 15:19:49 +09:00
Yang Rong 98887140e3 intel: Export pooled EU and min no. of eus in a pool.
Update kernel interface with new I915_GETPARAM ioctl entries for
pooled EU and min no. of eus in a pool. Add a wrapping function
for each parameter. Userspace drivers need these values when decide
the thread count. This kernel enabled pooled eu by default for BXT
and for fused down 2x6 parts it is advised to turn it off.

But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled and the no. of eus in a pool is different,
So userspace need to know min no. of eus in a pool.

V2: use return value as the query results.
    ret < 0 when error, ret = 0 when not support, and ret > 0 indicate
    query results.(Chris)
V3: Correct V2 errors.

Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-07 13:50:23 +01:00
Andreas Boll a5446775f2 automake: Don't include Android Makefiles in the release tarball
Currently only some Android Makefiles are included in the release tarball.
To be more consistent one could either add the remaining files or don't
ship Android Makefiles altogether.

According to Emil the Android folk doesn't use our release tarballs.
Thus it makes sense to remove those files from distribution which also
means less work for maintenance in the future.

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-07-23 09:45:53 +02:00
Rob Herring d342cd34ac Android: strip out header files from sources list
AOSP master now errors if LOCAL_SRC_FILES contains headers, so filter
out header files from the source lists.

Signed-off-by: Rob Herring <robh@kernel.org>
2016-07-06 16:58:38 +01:00
Rodrigo Vivi 7996a8707e intel: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.

However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.

So it is better removing them before they become used in any
other future platform.

v2: Rebase.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-06-29 10:23:37 -07:00
Rodrigo Vivi 22b6e33fe2 intel: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs.

v2: Avoid using "H" instead of HALO to keep names uniform - DK.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-06-29 10:22:52 -07:00
Michał Winiarski e3623d34ca intel/skl: Add missing SKL PCI IDs
Used by production devices:
    Intel(R) HD Graphics 510
    Intel(R) HD Graphics 535
    Intel(R) Iris(TM) Graphics 550
    Intel(R) Iris(TM) Graphics P555

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-27 17:45:34 -07:00
Eric Engestrom 723a6944c0 intel: Fix spelling mistakes
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-04-07 18:15:56 +01:00
Rodrigo Vivi ea07de92da intel: Adding missing Broxton PCI IDs.
These IDs were already part of the kernel since:

kernel commit 985dd4360fdf2533fe48a33a4a2094f2e4718dc0
Author: Imre Deak <imre.deak@intel.com>
Date:   Thu Jan 28 16:04:12 2016 +0200

    drm/i915/bxt: update list of PCIIDs

Cc: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
2016-03-02 14:27:30 -08:00
Marek Olšák 5198f2b2e6 configure.ac: disable annoying warning -Wmissing-field-initializers
It warns for all "{}" initializers.

Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-20 02:14:03 +01:00
Rodrigo Vivi 242f77ce03 intel/kbl: Add Kabylake PCI ids
Also, following kernel definition Kabylake is skylake.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2016-01-06 11:56:42 -08:00
Michał Winiarski b38a4b2326 intel: Restore formatting of offsets in debug statements
Using lower_32_bits and upper_32_bits macros was accidentally dropped in:

    commit 8b4d57e7b7
    Author: Michał Winiarski <michal.winiarski@intel.com>
    Date:   Wed Sep 9 16:07:10 2015 +0200

	intel: Add support for softpin

Let's restore previous, more readable format.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-22 01:58:33 -08:00
Kristian Høgsberg Kristensen d6ffb99726 intel: Add drm_intel_bo_set_softpin_offset to intel-symbol-check
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14 11:39:19 -08:00
Michał Winiarski 8b4d57e7b7 intel: Add support for softpin
Softpin allows userspace to take greater control of GPU virtual address
space and eliminates the need of relocations. It can also be used to
mirror addresses between GPU and CPU (shared virtual memory).
Calls to drm_intel_bo_emit_reloc are still required to build the list of
drm_i915_gem_exec_objects at exec time, but no entries in relocs are
created. Self-relocs don't make any sense for softpinned objects and can
indicate a programming errors, thus are forbidden. Softpinned objects
are marked by asterisk in debug dumps.

Cc: Thomas Daniel <thomas.daniel@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Zou Nanhai <nanhai.zou@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2015-12-14 11:31:25 -08:00
Michel Thierry 5453f89b70 intel: add drm_intel_bo_use_48b_address_range to symbol-check test
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14 11:31:25 -08:00
Michel Thierry 3350add5cc intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.

In specific, any resource used with flat/heapless (0x00000000-0xfffff000)
General State Heap (GSH) or Instruction State Heap (ISH) must be in a
32-bit range, because the General State Offset and Instruction State Offset
are limited to 32-bits.

The i915 driver has been modified to provide a flag to set when the 4GB
limit is not necessary in a given bo (EXEC_OBJECT_SUPPORTS_48B_ADDRESS).
48-bit range will only be used when explicitly requested.

Callers to the existing drm_intel_bo_emit_reloc function should set the
use_48b_address_range flag beforehand, in order to use full ppgtt range.

v2: Make set/clear functions nops on pre-gen8 platforms, and use them
    internally in emit_reloc functions (Ben)
    s/48BADDRESS/48B_ADDRESS/ (Dave)
v3: Keep set/clear functions internal, no-one needs to use them directly.
v4: Don't set 48bit-support flag in emit reloc, check for ppgtt type
    before enabling set/clear function, print full offsets in debug
    statements, using port of lower_32_bits and upper_32_bits from linux
    kernel (Michał)

References: http://lists.freedesktop.org/archives/intel-gfx/2015-July/072612.html
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-12-14 11:31:19 -08:00
Chih-Wei Huang 42f2f92059 intel: add the missing <strings.h> include
It defines the prototype of ffs that fixes the building error
on Android 6.0 64-bit image.

Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-01 16:48:17 +00:00
Ben Widawsky 4309bfd9f8 intel: Cleanup SKL PCI ID definitions.
This removes ones which aren't used, and adds some new ones. I kept the original
names where possible.

Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-11-03 11:19:13 -08:00
Ben Widawsky cad0e03f5a intel: Add SKL GT4 PCI IDs
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-11-03 11:19:06 -08:00
Emil Velikov 23667f566a intel: ignore missing-field-initializers warnings
We're about to remove the -Wno flag from configure.ac which will lead
to a lot of unnecessary spam.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-09-04 21:39:06 +01:00
Emil Velikov 0ec7f4423d intel: introduce to_bo_gem() helper
...to minimise misuse of bo_gem.
If the variable is declared at the top of the function and then used
for two (or more) different contexts this can cause confusion and errors.

Just introduce a wrapper, which can be used in a once off situations.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by Chris Wilson <chris@chris-wilson.co.uk>
2015-09-04 21:39:01 +01:00
Emil Velikov 94425f6272 intel: error out on has_error in exec2
Just like we do for the original exec()

v2: move bo_gem declaration to the top of the function.

Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by Chris Wilson <chris@chris-wilson.co.uk>
2015-09-04 21:38:56 +01:00
Emil Velikov cf7e32bdf9 intel: resolve shadowing warnings
v2: keep the bo_gem declaration in exec2() within the loop (Chris)

Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by Chris Wilson <chris@chris-wilson.co.uk>
2015-09-04 21:38:51 +01:00
Rafał Sapała cf40cf05a4 intel: Serialize drmPrimeFDToHandle with struct_mutex
It is possible to hit a race condition in create_from_prime, when trying
to import a BO that's currently being freed. In case of prime sharing
we'll succesfully get a handle, but fail on get_tiling call, potentially
confusing the caller (and requiring different locking scheme than with
sharing using flink). Wrap fd_to_handle with struct_mutex to force
a more consistent behaviour between prime/flink, convert fprintf to DBG
when handling errors.

(From Chris:
  The race is that the kernel returns us the same file-private handle as
  the first thread, but that first thread is about to call gem_close
  (thereby removing the handle from the file completely) and does so
  between us acquiring the handle and taking the mutex. If we take
  the mutex, then we acquire the refcnt on the bo prior to the first
  thread completing its unref (and so preventing the early close). Or we
  acquire the handle after the earlier close, in which case we are the new
  owner.
)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Testcase: igt/drm_import_export/import-close-race-prime
Signed-off-by: Rafał Sapała <rafal.a.sapala@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
2015-08-21 14:43:23 +01:00
Tapani Pälli f1468e8846 intel: wrap intel_bufmgr.h C code for C++ compilation/linking
We need this include in porting changes for the OpenGL ES
conformance suite.

v2: remove c_plusplus usage

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-08-10 11:26:16 +03:00
Kristian Høgsberg Kristensen cd2f91e18d intel: Drop aub dumping functionality
We now have a separate tool for this in intel-gpu-tools and we don't
need to clutter up libdrm with this feature. We leave the entry points
in there to avoid breaking API/ABI.

Install intel-gpu-tools, then run (for example)

    $ intel_aubdump --output=trace.aub glxgears -geometry 500x500

See the intel_aubdump man page for more details.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-08-03 09:19:47 -07:00
Emil Velikov c08655271a Consistently check the fd value
Follow the approach used through the rest of the project.

Suggested-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
2015-07-16 16:41:53 +01:00
Anuj Phogat 5ba34e1aee Set alignment value in drm_intel_add_validate_buffer()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-07-06 15:38:05 -07:00
Anuj Phogat 5c68f9f6f9 i965/gen9: Pass alignment as function parameter in drm_intel_gem_bo_alloc_internal()
In case of YF/YS tiled buffers libdrm need not know about the tiling
format because these buffers don't have hardware support to be tiled
or detiled through a fenced region. But, libdrm still need to know
about buffer alignment restrictions because kernel uses it when
resolving the relocation.

Mesa uses drm_intel_gem_bo_alloc_for_render() to allocate Yf/Ys buffers.
So, use the passed alignment value in this function to initialize the
align variable in drm_intel_bo. Note that we continue ignoring the
alignment value passed to drm_intel_gem_bo_alloc() to follow the
previous behavior.

V2: Add a condition to avoid allocation from cache. (Ben)
V3: Make no changes in cache allocation strategy. Just update the alignment.
    Update the aperture size estimate including the alignment. (Ben, Chris)
V4: Move aperture size adjustments inside drm_intel_bo_gem_set_in_aperture_size()
    Don't split sentences across the one-line header and the changelog. (Chris)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2015-07-06 15:36:59 -07:00
Damien Lespiau e9ea1f42d1 intel: Add the Broxton PCI IDs
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2015-05-18 16:24:21 +01:00
Tvrtko Ursulin 30921483c7 intel: Leak the userptr test bo
In order to use userptr, the kernel tracks the owner's mm with a
mmu_notifier. Setting that is very expensive - it involves taking all
mm_locks and a stop_machine(). This tracking lives only for as long as
the client is using userptr objects - so if the client allocates then
frees a userptr in a loop, we will be executing that heavyweight setup
everytime. To ammoritize this cost, just leak the test bo and the single
backing page we use for detecting userptr.

v2: Free the object and memory when bufmgr is destroyed.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2015-04-29 15:22:58 +01:00
Emil Velikov 41eb131dfe drm: use c99 __func__ over __FUNCTION__
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:21:02 +01:00
Emil Velikov e59f00fb43 configure: request/set the compiler in C99 mode
Required by intel and drmstat at least. Considering that every compiler
used to build libdrm is C99 compatible, just enable it for the whole
build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:20:52 +01:00
Emil Velikov 0f8da82500 drm: remove drm_public macro
Some compilers (like the Oracle Studio), require that the function
declaration must be annotated with the same visibility attribute as the
definition. As annotating functions with drm_public is no longer
required just remove the macro.

Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:19:15 +01:00
Emil Velikov 104c895f65 drm: remove no longer needed VISIBILITY_CFLAGS
With earlier commits we've annotated the private symbols, thus
we no longer require the -fvisibility=hidden CFLAGS.

Cc: Ben Skeggs <bskeggs@redhat.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:19:15 +01:00
Emil Velikov 42465feb97 drm: rename libdrm{,_macros}.h
Provide a more meaningful name, considering what it does.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:19:15 +01:00
Emil Velikov a418f2f895 intel: add symbols test
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:19:15 +01:00
Emil Velikov 5966d37732 intel: annotate the private symbols
They are less and easier to track than the public ones. The macro
drm_public will be going away by the end of the series.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:19:15 +01:00
Emil Velikov 1756d3d64b intel: remove unused mmFindBlock
The function was never part of the public API and a release or so back
was hidden from the global name-space (list of exported symbols).

According to git log this function was never used internally.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:19:13 +01:00
Emil Velikov 8e76f63cc4 intel: remove the drm_mm* symbol workarounds
Added with commit 57b4c4c32d3(Move the renaming of mm.c symbols to
symbol duplication/collision with ones that are available elsewhere.

As the public/private symbols of libdrm are properly annotated neither
one of the symbols will end up in the global name-space, thus should no
longer be required.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-28 11:18:43 +01:00