Ben Skeggs
9a999e57af
nouveau: crappy ttm mm init, disabled for now.
2007-11-05 01:20:32 +11:00
Jeremy Kolb
2dc2ee7a5a
nouveau: put it all together.
2007-11-02 19:47:48 -04:00
Dave Airlie
bb5f2158db
radeon: set the address to access the aperture on the CPU side correctly
...
This code relied on the CPU and GPU address for the aperture being the same,
On some r5xx hardware I was playing with I noticed that this isn't always true.
I wonder if this will fix some of those r4xx DRI issues we've seen in the past.
2007-11-03 00:39:44 +10:00
Jesse Barnes
128a8f7ea2
Use unsigned long instead of u64 in drm_modeset_ctl_t
...
A bad idea, ABI-wise, but we're going to be changing this structure anyway
before we merge upstream, so just fix the build for now.
2007-11-01 15:02:26 -07:00
Stephane Marchesin
5766d81074
nouveau: don't use AGP on PPC. It's a hopeless case.
2007-11-01 15:49:10 +01:00
Jeremy Kolb
9416541fb2
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm
2007-10-31 20:14:48 -04:00
Jeremy Kolb
31847b4b62
nouveau: ttm stubs
2007-10-31 20:13:01 -04:00
Dave Airlie
61cbcb5dbe
drm/ttm: add support for cached un-snooped mappings.
...
This mapping allows cached objects to be mapped in/out of the TT space
with the appropriate flushing calls.
It should put back the old CACHED functionality for snooped mappings
2007-11-01 10:34:53 +11:00
Dave Airlie
17f0882d50
drm: add chipset flushing via agp support
2007-10-31 11:33:34 +11:00
Dave Airlie
2489062a33
i915: add backwards compat chipset flushing code
2007-10-31 11:27:44 +11:00
Jesse Barnes
91aae7e683
Merge branch 'master' into vblank-rework, fixup remaining drivers
...
Conflicts:
linux-core/drmP.h
linux-core/drm_drv.c
linux-core/drm_irq.c
shared-core/i915_drv.h
shared-core/i915_irq.c
shared-core/mga_drv.h
shared-core/mga_irq.c
shared-core/radeon_drv.h
shared-core/radeon_irq.c
Merge in the latest master bits and update the remaining drivers (except
mach64 which math_b is working on). Also remove the 9xx hack from the i915
driver; it seems to be correct.
2007-10-30 12:52:46 -07:00
Stephane Marchesin
79744d730c
Nouveau: add a comment about SKIPS for next API breakage.
2007-10-30 16:55:17 +01:00
Stephane Marchesin
0cebcd43dd
Nouveau: fold some loops.
2007-10-30 16:54:57 +01:00
Dave Airlie
50dec29c80
drm/i915: add driver cache flush entry point
...
Use clflush on Intel hardware to flush cached objects.
2007-10-30 17:52:13 +10:00
Kristian Høgsberg
ff5889f831
Move struct drm_drawable_info out of public header file.
2007-10-29 19:32:46 -04:00
Jesse Barnes
6342e0507b
Remove unused memory save areas
...
These need to be kmalloc'd separately anyway or we may hit kmalloc size
limits.
2007-10-29 10:51:11 -07:00
Stephane Marchesin
cc745fcc3a
nouveau: don't touch PMC_BOOT_1 on x86, it seems to be undefined on some early cards.
2007-10-28 01:59:39 +02:00
Jesse Barnes
1e2a2babab
i915: suspend/resume support
...
Add suspend/resume support to the i915 driver. Moves some of the
initialization into the driver load routine, and fixes up places where we
assumed no dev_private existed in some of the cleanup paths. This allows
us to suspend/resume properly even if X isn't running.
2007-10-26 16:10:02 -07:00
Stephane Marchesin
b9d8ddd3ca
nouveau: flip the CHECK_STATE bit off on nv30. This lets you do 8-bit surface destination.
2007-10-26 15:12:04 +02:00
Ian Romanick
7e9ea55a2f
Initial pass at porting MGA to vblank-rework
...
This is currently only compile tested.
2007-10-25 17:14:53 -07:00
Thomas Hellstrom
b9d9c30474
Tighten permissions on some buffer manager ioctls.
...
Set bo init minor to 0.
Add the version function to header.
2007-10-25 10:29:15 +02:00
Thomas Hellstrom
11f3e5e53f
Buffer manager:
...
Implement a version check IOCTL for drivers that don't use
drmMMInit from user-space.
Remove the minor check from the kernel code. That's really up
to the driver.
Bump major.
2007-10-25 10:12:21 +02:00
Thomas Hellstrom
07706c9b79
Merge branch 'master' into drm-ttm-finalize
2007-10-25 09:24:45 +02:00
Dave Airlie
a70fe82baf
i915: relocate buffers before validation add memory barrier between two
2007-10-25 16:53:18 +10:00
Dave Airlie
c5f158abbe
i915: remove relocatee kernel mapping sooner stops mutex taking during sleep
2007-10-25 16:52:33 +10:00
Eric Anholt
83199c257e
Fix missing \n on some DRM_ERROR in i915_dma.c
2007-10-24 16:27:51 -07:00
Dave Airlie
fd7c24753c
i915: use a drm memory barrier define
2007-10-24 11:13:15 +11:00
Dave Airlie
a294aa724a
i915: require mfence before submitting batchbuffer
2007-10-23 17:54:07 +10:00
Stephane Marchesin
9a115080e8
nouveau: fix IGP
2007-10-23 02:19:17 +02:00
Thomas Hellstrom
919c886b2b
A cmdbuf mutex to implement validate-submit-fence atomicity in the absence
...
of a hardware lock.
2007-10-22 18:59:37 +02:00
Dave Airlie
22883ff26b
i915: split reloc execution into separate function
2007-10-22 11:54:41 +11:00
Thomas Hellstrom
9ddff6d15f
Adapt i915 super-ioctl for lock-free operation.
2007-10-21 12:26:26 +02:00
Thomas Hellstrom
3b19b50cb5
Remove the need for the hardware lock in the buffer manager.
...
Add interface entry cleaning a memory type without touching NO_EVICT buffers.
2007-10-21 12:20:56 +02:00
Thomas Hellstrom
48b5eaf303
Simple replacement for hardware lock in some cases.
...
Fix i915 since last commit.
2007-10-20 16:49:43 +02:00
Thomas Hellstrom
086c058a41
Remove the op ioctl, and replace it with a setuser ioctl.
...
Remove need for lock for now.
May create races when we clean memory areas or on takedown.
Needs to be fixed.
Really do a validate on buffer creation in order to avoid problems with
fixed memory buffers.
2007-10-17 10:59:48 +02:00
Thomas Hellstrom
0d1926d36e
Revert "Replace NO_MOVE/NO_EVICT flags to buffer objects with an ioctl to set pinning."
...
This reverts cf2d569dac
commit.
2007-10-17 10:59:48 +02:00
Thomas Hellstrom
646560d1d1
Revert "Add some more verbosity to drm_bo_set_pin_req comments."
...
This reverts e7bfeb3031
commit.
2007-10-17 10:59:48 +02:00
Dave Airlie
ec1162b212
i915: lock struct mutex about buffer object lookups
2007-10-17 15:36:14 +10:00
Kristian Høgsberg
a69c85fec8
Drop destroy ioctls for fences and buffer objects.
...
We now always create a drm_ref_object for user objects and this is then the only
things that holds a reference to the user object. This way unreference on will
destroy the user object when the last drm_ref_object goes way.
2007-10-16 22:03:05 +11:00
Kristian Høgsberg
dccefba71a
Take bo type argument out of the ioctl interface.
...
The buffer object type is still tracked internally, but it is no longer
part of the user space visible ioctl interface. If the bo create ioctl
specifies a non-NULL buffer address we assume drm_bo_type_user,
otherwise drm_bo_type_dc. Kernel side allocations call
drm_buffer_object_create() directly and can still specify drm_bo_type_kernel.
Not 100% this makes sense either, but with this patch, the buffer type
is no longer exported and we can clean up the internals later on.
2007-10-16 22:03:05 +11:00
[utf-8] Kristian Høgsberg
440fc5113e
Eliminate support for fake buffers.
2007-10-16 21:59:38 +11:00
Ben Skeggs
9fdab5b5c5
nouveau: revert unintended change.
2007-10-16 14:43:57 +11:00
Ben Skeggs
677753047f
nouveau: Cleanup PGRAPH handler, attempt to survive PGRAPH exceptions.
2007-10-16 14:42:26 +11:00
Ben Skeggs
3af053779c
nouveau: Survive PFIFO_CACHE_ERROR.
2007-10-16 13:32:03 +11:00
Ben Skeggs
6398325ba1
nouveau: Handle multiple PFIFO exceptions per irq, cleanup output.
2007-10-16 13:27:27 +11:00
Stephane Marchesin
30353c8efc
nouveau: PPC fixes. These regs are very touchy.
2007-10-14 23:08:36 +02:00
Jeremy Kolb
837e364353
nouveau: fix warning.
2007-10-14 10:56:31 -04:00
Jeremy Kolb
811e43f9e2
nouveau: fix warning.
2007-10-14 10:56:17 -04:00
Dave Airlie
8d3cb7e472
i915: fix vbl_swap allocation
2007-10-14 21:19:13 +10:00
Pekka Paalanen
3ab7627651
nouveau: Fix a typo in nv25_graph_context_init
2007-10-12 23:55:59 +03:00
Stuart Bennett
50deb31e9f
nouveau: Fix typos in nv20_graph_context_init
2007-10-12 23:49:51 +03:00
Pekka Paalanen
0d2554f83e
nouveau: Make notifiers go into PCI memory
...
On some hardware notifers in AGP memory just don't work.
2007-10-12 23:47:14 +03:00
Arthur Huillet
9d779e2c88
nouveau: mandatory "oops I forgot half of the files" commit
2007-10-12 22:40:08 +02:00
Arthur Huillet
74ea019863
nouveau: added support for software methods, and implemented those necessary for NV04 (TNT1) to start X
2007-10-12 22:36:55 +02:00
Dave Airlie
74001c34e5
i915: add superioctl support to i915
...
This adds the initial i915 superioctl interface. The interface should be
sufficent even if the implementation may needs fixes/optimisations internally
in the drm wrt caching etc.
2007-10-12 10:54:38 +10:00
Matthieu Castet
bf126f4925
nouveau : nv10 and nv04 PGRAPH_NSTATUS are different
2007-10-10 21:11:43 +02:00
Maarten Maathuis
d912709a63
nouveau: PMC_BOOT_1 was not mapped.
2007-10-10 16:41:21 +02:00
Stephane Marchesin
9b294bbe0e
nouveau: try to fix big endian.
2007-10-10 01:12:20 +02:00
Maarten Maathuis
20928a2f2b
nouveau: A char is signed, so it may overflow for >NV50.
2007-10-07 19:01:58 +02:00
Matthieu Castet
18952a1670
nouveau : print correct value in nouveau_graph_dump_trap_info for nv04
2007-10-06 12:01:02 +02:00
Dave Airlie
19b7cc3444
Merge branch 'pre-superioctl-branch'
2007-10-05 12:11:43 +10:00
Maarten Maathuis
d351601899
nouveau: Remove excess device classes.
2007-10-04 09:46:16 +02:00
Maarten Maathuis
319436c5cc
nouveau: NV47 context switching voodoo + warning
2007-10-04 09:39:31 +02:00
Maarten Maathuis
b510517d59
nouveau: Switch over to using PMC_BOOT_0 for card detection.
2007-10-04 09:31:46 +02:00
Stephane Marchesin
7fbd10d933
nouveau: nv2a drm context switch support.
2007-10-04 03:44:23 +02:00
Pekka Paalanen
a72eb27fbc
nouveau: nv20 graph_create_context difference
...
nv20 writes the chan->id to a different place than nv28.
This still does not make nv20 run nv10_demo.
2007-10-02 22:18:47 +03:00
Pekka Paalanen
afc57ef1df
nouveau: fix nv25_graph_context_init
...
It was writing 4x the data in a loop.
2007-10-02 22:18:47 +03:00
Stuart Bennett
ffa3173ec4
nouveau: nv20 graph context init
2007-10-02 22:18:46 +03:00
Maarten Maathuis
69fcfb413e
nouveau: Fix dereferencing a NULL pointer when erroring out during initialization.
2007-10-01 22:21:23 +02:00
Stephane Marchesin
e1600646a9
nouveau: flip the ctx switch bit on. it seems to be ignored on nv34 but causes nv30 issues.
2007-10-01 03:28:10 +02:00
Matthieu Castet
75e8f4b5cf
nouveau : nv30 remove harcoded NV20_PGRAPH_CHANNEL_CTX_TABLE
2007-09-30 23:19:39 +02:00
Matthieu Castet
9cd6ece307
nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idle
...
Also clean PGRAPH_CHANNEL macros
2007-09-30 23:09:30 +02:00
Pekka Paalanen
aa135ba8e8
nouveau: rename nv30_graph.c to nv20_graph.c
2007-09-30 22:16:01 +03:00
Pekka Paalanen
205403aea8
nouveau: nv30 graph function renames, removed nv20_graph.c
...
All nv30 functions in nv30_graph.c that can be used on nv20 are renamed
as accordingly. nv20 specific parts from nv20_graph.c are moved into
nv30_graph.c.
2007-09-30 22:16:01 +03:00
Pekka Paalanen
a67060c810
nouveau: graph ctx init nv25
...
According to mmio_trace_900XGL.tar.bz2 by Evan Fraser the nv25 init is
exactly the same as nv28 init.
2007-09-30 22:16:01 +03:00
Pekka Paalanen
aa2c337991
nouveau: nv28 graph context init
2007-09-30 22:16:01 +03:00
Pekka Paalanen
8ad605a264
nouveau: let nv20 hardware do ctx switching automatically.
2007-09-30 22:16:01 +03:00
Pekka Paalanen
dc592c8b7b
nouveau: Make nv20 use the nv30 PGRAPH ctx functions.
2007-09-30 22:16:01 +03:00
Pekka Paalanen
88bdb38cea
nouveau: Change couple constants to symbols.
2007-09-30 22:16:01 +03:00
Pekka Paalanen
a45fce7712
nouveau: NV30 should never call nouveau_nv20_context_switch().
2007-09-30 22:16:01 +03:00
Matthieu Castet
fb3ed99fb1
nouveau : pgraph_ctx dynamic alloc for nv04, nv10
2007-09-30 14:50:22 +02:00
Matthieu Castet
c76e04828b
nouveau : nv04 don't use chan->pgraph_ctx array
...
This commit is a first step to dynamic alloc pgraph context on nv04, nv10.
2007-09-30 14:21:47 +02:00
Matthieu Castet
f8f31f0457
nouveau : stop the fifo of the channel we are deleting
2007-09-29 23:07:29 +02:00
Matthieu Castet
097db7a9b0
nouveau : nv1x fix strange corruption
...
that appears when running glxgears and nouveau demo
2007-09-29 23:07:29 +02:00
chaohong guo
f863d23e01
radeon: Commit the ring after each partial texture upload blit.
...
This makes sure each blit starts as early as possible, which may improve
texture upload performance in some cases.
2007-09-29 18:08:04 +02:00
Matthieu Castet
72134e939e
nouveau : clean chan->pgraph_ctx stuff. We now do a static init of the array.
...
This avoid hardcoding pgraph_ctx size and potential buffer overflow.
2007-09-28 21:29:58 +02:00
Jesse Barnes
0bb2395a8b
Revert drm_i915_flip_t braindamage
...
I should not have renamed this field.
I should not have renamed this field.
I should not have renamed this field.
On the plus side, it was at least binary compatible.
2007-09-28 10:10:08 -07:00
Thomas Hellstrom
c4b3a0f602
Merge branch 'master' into pre-superioctl-branch
...
Conflicts:
linux-core/drm_bo.c
linux-core/drm_fence.c
linux-core/drm_objects.h
shared-core/drm.h
2007-09-25 18:03:31 +02:00
Dave Airlie
03c47f1420
drm: use fence_class as name instead of class
2007-09-25 16:17:17 +10:00
Thomas Hellstrom
da63f4ba0f
Add fence error member.
...
Modify the TTM backend bind arguments.
Export a number of functions needed for driver-specific super-ioctls.
Add a function to map buffer objects from the kernel, regardless of where they're
currently placed.
A number of error fixes.
2007-09-22 13:57:13 +02:00
Eric Anholt
24e33627c5
Merge branch 'bo-set-pin'
...
This branch replaces the NO_MOVE/NO_EVICT flags to buffer validation with a
separate privileged ioctl to pin buffers like NO_EVICT meant before. The
functionality that was supposed to be covered by NO_MOVE may be reintroduced
later, possibly in a different way, after the superioctl branch is merged.
2007-09-21 17:12:19 -07:00
Eric Anholt
e7bfeb3031
Add some more verbosity to drm_bo_set_pin_req comments.
2007-09-21 16:14:22 -07:00
Stephane Marchesin
7587e9682c
nouveau: fix ppc and get it right this time.
2007-09-21 22:42:39 +02:00
Stephane Marchesin
dc60c452e6
nouveau: fix notifiers on PPC.
2007-09-21 22:27:53 +02:00
Stephane Marchesin
74c6f2f47a
nouveau: add some checks to the nv04 graph switching code.
2007-09-21 22:04:50 +02:00
Eric Anholt
3d3a96ad4e
Merge branch 'origin' into bo-set-pin
2007-09-19 15:55:58 -07:00
Michel Dänzer
e349b58b4a
i915: Reinstate check that drawable has valid information in i915_vblank_swap.
2007-09-18 21:06:55 +01:00
Michel Dänzer
78d111fa96
i915: Fix scheduled buffer swaps.
...
One instance of unlocking a spinlock was converted incorrectly when this code
was fixed to build on BSD.
2007-09-18 21:06:55 +01:00
Ian Romanick
a3881ad2fe
Add ioc32 compat layer for XGI DRM.
2007-09-18 11:03:49 -07:00
Jesse Barnes
852232fb80
Remove plane->pipe mapping from SAREA private after all
...
We can figure out which pipe a given plane is mapped to by looking at the
display control registers instead of tracking it in a new SAREA private field.
If this becomes a performance problem, we could move to an ioctl based solution
by adding a new parameter for the DDX to set (defaulting to the old behavior if
the param was never set of course).
2007-09-12 08:55:33 -07:00
Jesse Barnes
7fdf98051a
Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/drm
2007-09-11 03:50:17 -07:00
Jesse Barnes
3cb8acd5ab
Disambiguate planes & pipes for swap operations
...
This mod makes the SAREA track plane to pipe mappings and corrects the name of
the plane info variables (they were mislabeled as pipe info since until now all
code assumed a direct mapping between planes and pipes).
It also updates the flip ioctl argument to take a set of planes rather than
pipes, since planes are flipped while pipes generate vblank events.
2007-09-11 03:48:46 -07:00
Patrice Mandin
0bd8752a0c
nouveau: nv10: add combiner registers
2007-09-10 18:53:48 +02:00
Matthieu Castet
00bb534a54
nouveau : nv10 fix NV10_PGRAPH_CTX_USER save/load
2007-09-09 15:49:33 +02:00
Matthieu Castet
b2ee72f440
nouveau : nv10 pipe ctx switch load/save.
...
This fix some issues with more than one 3D fifo, but there still some "corruption" sometimes
2007-09-09 12:13:00 +02:00
Maarten Maathuis
f19d80b046
nouveau: Add Quadro NVS 140 pciid
2007-09-08 22:19:00 +02:00
Ben Skeggs
06bb072595
nouveau: Use nv41 ctxprog/vals on nv42.
2007-09-07 20:07:13 +10:00
Ian Romanick
54c96cbc46
Merge branch 'xgi-0-0-2'
2007-09-06 15:37:52 -07:00
Stephane Marchesin
edf5a86a26
nouveau: fix some nv04 graph switching.
2007-09-06 02:47:06 +02:00
Stephane Marchesin
ff9a019cf0
nouveau: add pure nv30 support.
2007-09-06 02:47:06 +02:00
Maarten Maathuis
ef4944de85
Add context init voodoo and context switch code for NV41.
2007-09-04 18:51:57 +02:00
Ian Romanick
fee49e2071
Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into xgi-0-0-2
2007-08-31 10:54:55 -07:00
Stephane Marchesin
bac3f49daa
nouveau: nv04 context switching support. Works for starting X up at least.
2007-08-31 01:40:00 +02:00
Stephane Marchesin
69b11f44f0
nouveau: give nv03 the last cut.
2007-08-31 01:40:00 +02:00
Keith Packard
c78e610fa4
Add register defines for hw binning
2007-08-28 12:23:51 -07:00
Dave Airlie
589707b765
drm: remove XFREE86_VERSION macros
2007-08-28 15:17:36 +10:00
Matthieu Castet
a331d2e352
nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition
...
- fix offset for nv04
- use it in nv10 graph ctx switch for getting next channel
- dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-26 20:48:32 +02:00
Matthieu Castet
4182fce408
nouveau : nv1x graph reworks
...
- add forgotten init value
- use the same PGRAPH_DEBUG than the blob
- remove init of ddx reg : it should be done with object
- better handle of channel destruction
hope I didn't break anything ;)
2007-08-25 22:10:45 +02:00
Patrice Mandin
502bbdbe14
nouveau: nv10: output a warning if last channel invalid, and switch to next
2007-08-25 00:12:58 +02:00
Patrice Mandin
9875011196
nouveau: nv10: check some NULL pointers inside context switch
2007-08-23 10:20:44 +02:00
Matthieu Castet
8645dac895
nouveau : fix some potential crashes with objects causing hash collision
2007-08-22 23:20:14 +02:00
Ben Skeggs
11c46afe75
nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do.
2007-08-22 13:23:49 +10:00
Ben Skeggs
a654c0341a
nouveau/nv40: Dump extra info on ucode state if ctx switch fails.
2007-08-22 13:19:21 +10:00
Ben Skeggs
81eaff44c4
nouveau: NV4c ctx ucode.
...
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the
ucode matches it still.
2007-08-22 13:09:27 +10:00
Ben Skeggs
ae883c97ad
nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit.
2007-08-22 12:54:26 +10:00
Stephane Marchesin
c8ee6a6cab
nouveau: redo nv30_graph.c. Should work better, but we still lack a couple of cards.
2007-08-22 04:20:50 +02:00
Stephane Marchesin
76337bdb19
nouveau: fix the comment and debug message for PCIGART size
2007-08-22 04:20:50 +02:00
Ben Skeggs
03c0490129
nouveau: Add NV44 ctx ucode. Patch from stillunknown.
...
Microcode is similar enough to the NV4A one that it should be able to use
the same initial PGRAPH context. One day this mess will go away, honest..
2007-08-21 02:23:21 +10:00
Ben Skeggs
216f1b0573
nouveau: Poke 0x2230 on NV47 also.
...
Makes 0x2220 work the same way as on NV40.
2007-08-21 02:18:27 +10:00
Patrice Mandin
c8760c7999
Check also for Linux, as it's not supported on different OS
2007-08-19 18:45:01 +02:00
Patrice Mandin
a122e7dabf
Function pci_get_bus_and_slot needs 2.6.19 or later
2007-08-19 18:41:18 +02:00
Eric Anholt
0055fd5c35
Merge branch 'master' into bo-set-pin
2007-08-16 09:23:09 -07:00
Ben Skeggs
8a4d7f34d9
nouveau: Detect memory on NFORCE/NFORCE2 correctly.
2007-08-17 01:12:46 +10:00
Ben Skeggs
10f9b7bd0b
nouveau: Use count parameter in nouveau_notifier_alloc().
2007-08-15 14:14:23 +10:00
Ben Skeggs
a615d2fde7
nouveau: Turn some messages into DRM_DEBUGs..
2007-08-15 14:01:35 +10:00
Ben Skeggs
c3faa589b0
nouveau: Allow GART notifiers when using sgdma code.
2007-08-15 13:36:54 +10:00
Ben Skeggs
ee01d3755a
nouveau: Workaround mysterious PRAMIN clobbering by the card.
2007-08-15 13:34:57 +10:00
Ian Romanick
f563a50d14
Eliminate unused / useless ioctls.
2007-08-14 13:44:51 -07:00
Ben Skeggs
a6ea60c77e
nouveau: Catch all NV4x chips instead of just NV_40.
2007-08-15 01:40:46 +10:00
Ben Skeggs
02c4e0e757
nouveau/nv40: Fix channel scheduling.
...
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels
will appear to "freeze" in some circumstances.
2007-08-15 01:04:41 +10:00
Dave Airlie
da27986870
i915: i965 non-secure batchbuffer bit has moved.
2007-08-11 08:57:53 +10:00
Ben Skeggs
a46104674f
nouveau/nv50: demagic instmem setup.
2007-08-10 14:22:50 +10:00
Ben Skeggs
39907f613b
nouveau: Allow creation of gpuobjs before any other init has taken place.
2007-08-10 13:53:10 +10:00
Ian Romanick
aea6b4dea9
Unify alloc and free ioctls.
...
The DRM_XGI_PCIE_ALLOC and DRM_XGI_FB_ALLOC ioctls (and the matching
free ioctls) are unified to DRM_XGI_ALLOC. The desired memory region
is selected by xgi_mem_alloc::location. The region is magically
encoded in xgi_mem_alloc::index, which is used to release the memory.
Bump to version 0.11.0. This update requires a new DDX.
2007-08-09 15:30:36 -07:00
Ben Skeggs
7784e8c6e7
nouveau: silence irq handler a bit
2007-08-09 11:12:13 +10:00
Ben Skeggs
7281463f8d
nouveau/nv40: add some missing pciids.
2007-08-09 10:23:36 +10:00
Matthieu Castet
e326acf549
nouveau : nv10, nv20, nv30 : don't save all channel in the same RAMFC entry
...
This should improve multi fifo
2007-08-08 22:55:32 +02:00
Ben Skeggs
05633ca370
nouveau: Always allocate drm's push buffer in VRAM
...
Fixes #11868
2007-08-08 16:37:55 +10:00
Ben Skeggs
40f2156356
nouveau: return channel id
2007-08-08 16:12:19 +10:00
Ben Skeggs
296050eee6
nouveau/nv50: hack up initial channel context from current state
...
We really should be providing static values like the nv40 PGRAPH code does,
however, this will do for now to keep X at least working.
2007-08-08 13:01:29 +10:00
Ben Skeggs
4ad487190d
nouveau: enable/disable engine-specific interrupts in _init()/_takedown()
...
All interrupts are still masked by PMC until init is finished.
2007-08-08 10:49:05 +10:00
Matthieu Castet
a4759b8513
nouveau : fix enable irq (in the previous code all irq were masked by engine
...
init after irq_postinstall)
2007-08-07 23:09:44 +02:00
Ben Skeggs
66f5232d93
nouveau: Init global gpuobj list early, unbreaks sgdma code.
2007-08-07 01:52:49 +10:00
Stephane Marchesin
ac24f328ec
nouveau: Bump PCI GART to 16MB
2007-08-06 17:16:05 +02:00
Ben Skeggs
8d5a8ebc31
nouveau: ouch, add nouveau_dma.[ch] files..
2007-08-06 22:32:36 +10:00
Ben Skeggs
7a0a812ea4
nouveau: Remove PGRAPH_SURFACE hack, it wont work now anyway.
...
Need to find another way of doing this, ideally someone'd hunt down which
object/method controls it! The Xv blit adaptor is likely now broken on
cards that have pNv->WaitVSyncPossible enabled.
2007-08-06 22:09:15 +10:00
Ben Skeggs
cf04641bc6
nouveau: Give DRM its own gpu channel
...
If your card doesn't have working context switching, it is now broken.
2007-08-06 22:05:31 +10:00
Ben Skeggs
51f24be578
nouveau: Determine trapped channel id from active grctx on >=NV40
2007-08-06 21:46:55 +10:00
Ben Skeggs
97770db720
nouveau: Various internal and external API changes
...
1. DRM_NOUVEAU_GPUOBJ_FREE
Used to free GPU objects. The obvious usage case is for Gr objects,
but notifiers can also be destroyed in the same way.
GPU objects gain a destructor method and private data fields with
this change, so other specialised cases (like notifiers) can be
implemented on top of gpuobjs.
2. DRM_NOUVEAU_CHANNEL_FREE
3. DRM_NOUVEAU_CARD_INIT
Ideally we'd do init during module load, but this isn't currently
possible. Doing init during firstopen() is bad as X has a love of
opening/closing the DRM many times during startup. Once the
modesetting-101 branch is merged this can go away.
IRQs are enabled in nouveau_card_init() now, rather than having the
X server call drmCtlInstHandler(). We'll need this for when we give
the kernel module its own channel.
4. DRM_NOUVEAU_GETPARAM
Add CHIPSET_ID value, which will return the chipset id derived
from NV_PMC_BOOT_0.
4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06 21:45:18 +10:00
Ben Skeggs
beaa0c9a28
nouveau: Pass channel struct around instead of channel id.
2007-08-06 03:40:43 +10:00
Patrice Mandin
2453ba19b6
nouveau:nv10: fill and use load,save graph context functions
2007-08-03 23:06:39 +02:00
Arthur Huillet
f01026eae6
nouveau: creating notifier in PCI memory for PCIGART
2007-07-27 15:48:04 +02:00
Ian Romanick
c561cb4650
Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into xgi-0-0-2
...
Conflicts:
linux-core/drmP.h
linux-core/drm_scatter.c
2007-07-26 16:58:28 -07:00
Eric Anholt
cf2d569dac
Replace NO_MOVE/NO_EVICT flags to buffer objects with an ioctl to set pinning.
...
This cleans up the create/validate interfaces for this very uncommon path, and
makes pinned object creation much easier to use for the X Server.
2007-07-26 10:15:11 -07:00
Ian Romanick
887cb31ee9
Fix bug preventing X server from restarting.
...
The core DRM lastclose routine automatically destroys all mappings and
releases SG memory. XP10 DRM and DDX assumed this data stayed around
until module unload. xgi_bootstrap was reworked to recreate all these
mappings. In addition, the drm_addmap for the GART backing store was
moved into the kernel. This causes a change to the ioctl protocol and
a version bump.
2007-07-24 13:27:44 -07:00
Ian Romanick
877296ade0
xgi_mem_alloc::offset is a hardware offset, so it should be u32, not long.
2007-07-21 21:36:11 -07:00
Ian Romanick
5d6fdd9d79
Clean up xgi_cmd_info and associated code.
...
There were numerous unnecessary fields in xgi_cmd_info. The remaining
fields had pretty crummy names. Cut out the cruft, and rename the
rest. As a result, the unused parameter "triggerCounter" to
triggerHWCommandList can be removed.
2007-07-21 20:34:56 -07:00
Eric Anholt
5b38e13416
Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
...
The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures. This also means that XFree86 4.2.0 support for i810 DRM
is lost.
2007-07-20 18:16:42 -07:00
Eric Anholt
c1119b1b09
Replace filp in ioctl arguments with drm_file *file_priv.
...
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM. There is a 1:1 mapping, so this
should be a noop. This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
2007-07-20 13:39:45 -07:00
Eric Anholt
e39286eb5e
Remove DRM_ERR OS macro.
...
This was used to make all ioctl handlers return -errno on linux and errno on
*BSD. Instead, just return -errno in shared code, and flip sign on return from
shared code to *BSD code.
2007-07-20 12:53:52 -07:00
Ian Romanick
5ba94c2ab8
Initial pass at converting driver to DRM infrastructure.
2007-07-19 10:29:18 -07:00
Eric Anholt
f4e1c1d05c
FreeBSD warnings cleanup.
2007-07-19 06:46:13 -07:00
Eric Anholt
05204b9c8d
Merge branch 'origin'
2007-07-19 06:31:26 -07:00
Ben Skeggs
0c95d489ab
nouveau/nv50: get non-default push buffer sizes working.
2007-07-19 16:43:37 +10:00
Eric Anholt
33a50412c2
Add dry-coded DRM drawable private information storage for FreeBSD.
...
With this, all modules build again.
2007-07-18 14:22:49 -07:00
Pekka Paalanen
af4cfa624a
nouveau: Make nouveau_wait_for_idle() read PTIMER.
...
Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to
read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is
added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is
halted). The timeout was selected as 1 giga-ticks, which for me is 1s.
2007-07-18 14:23:41 +03:00
Pekka Paalanen
696bee093f
nouveau: Add read() method to Engine.timer.
...
This is not called from anywhere, yet.
2007-07-18 14:12:26 +03:00
Pekka Paalanen
0c77f5abea
nouveau: Add bitfield names for NSOURCE and NSTATUS.
...
Name strings and pretty-printing in nouveau_graph_dump_trap_info().
2007-07-18 14:00:04 +03:00
Pekka Paalanen
14ecf8d6c2
nouveau: Replace 0x00400104 and 0x00400108 with names.
...
NV03_PGRAPH_NSTATUS and NV03_PGRAPH_NSOURCE.
The prefix NV03 is chosen because nv10reg.h had no versioned prefix,
and the code using these registers does not check card_type.
2007-07-18 13:52:39 +03:00
Dave Airlie
a64b5d8d37
fix some missing whitespace/tab
2007-07-18 15:49:45 +10:00
Dave Airlie
6ad1df2176
drm: remove drm_u64_t, replace with uint64_t everwhere
...
This might break something, stdint.h inclusion in drm.h maybe required
but I'm not sure yet what platforms have it what ones don't.
2007-07-18 09:42:06 +10:00
Ian Romanick
8d60bf2f19
Add XP5 and XP10 PCI IDs.
2007-07-16 22:15:41 -07:00
Ian Romanick
2b6ea46513
Eliminate unnecessary structures and defines.
2007-07-16 21:11:22 -07:00
Ben Skeggs
875dd1e538
nouveau: Destroy PGRAPH context table on PGRAPH takedown
2007-07-17 14:06:05 +10:00
Ian Romanick
658ff2daf3
Eliminate several useless ioctls and associated cruft.
...
The ioctlss XGI_ESC_DEVICE_INFO, XGI_ESC_MEM_COLLECT,
XGI_ESC_PCIE_CHECK, XGI_ESC_GET_SCREEN_INFO, XGI_ESC_PUT_SCREEN_INFO,
XGI_ESC_MMIO_INFO, and XGI_ESC_SAREA_INFO, are completely unnecessary.
The will be doubly useless when the driver is converted to the DRM
infrastructure.
2007-07-16 20:58:43 -07:00
Ben Skeggs
ec67c2def9
nouveau: G8x PCIEGART
...
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
2007-07-17 13:51:14 +10:00
Ian Romanick
70a8a60a3e
Correct errors in the usage of pci_map_page.
...
With these changes the driver no longer instantly hard-locks a 6600LE
on a PowerPC G5. I haven't tested any 3D apps yet.
2007-07-16 10:56:43 -07:00
Eric Anholt
3f04fe7890
Fix FreeBSD build.
2007-07-16 01:53:06 -07:00
Dave Airlie
24311d5d82
drm: remove drm_buf_t
2007-07-16 13:42:11 +10:00
Dave Airlie
be85ad0333
drm: detypedef ttm/bo/fence code
2007-07-16 13:37:02 +10:00
Dave Airlie
6dce9e0735
drm: remove hashtab/sman and object typedefs
2007-07-16 12:48:44 +10:00
Dave Airlie
21ee6fbfb8
drm: remove drmP.h internal typedefs
2007-07-16 12:32:51 +10:00
Dave Airlie
1a07256d60
drm: remove ttm userspace typedefs
2007-07-16 11:30:53 +10:00
Dave Airlie
b95ac8b7b3
drm: detypedef drm.h and fixup all problems
2007-07-16 11:22:15 +10:00
Dave Airlie
f174f835ff
drm: remove typedefs in drm.h to their own section
2007-07-16 10:13:58 +10:00
Dave Airlie
2134193af6
Merge branch 'drm-ttm-cleanup-branch'
2007-07-16 10:05:20 +10:00
Patrice Mandin
bc7d6c76fa
nouveau: nv10 and nv11/15 are different
2007-07-14 18:32:11 +02:00
Arthur Huillet
aa6d9199fa
applied patch from Ian Romanick fixing PCI DMA object creation code
2007-07-13 20:51:52 +02:00
Arthur Huillet
5ae3ad4f01
now attempting to create PCI object only when there is a pci_heap
2007-07-13 16:00:03 +02:00
Ben Skeggs
0029713451
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-13 15:09:31 +10:00
Ian Romanick
5522136b7f
Merge branch 'master' into xgi-0-0-2
2007-07-12 15:28:17 -07:00
Ben Skeggs
851c950d98
nouveau: unbreak AGP
2007-07-13 02:18:59 +10:00
Ben Skeggs
af317f1cc7
nouveau: mem_alloc() returns offsets, not absolute addresses now.
2007-07-12 11:55:47 +10:00
Ben Skeggs
522a0c868c
nouveau: nuke left over debug message
2007-07-12 11:39:45 +10:00
Ben Skeggs
750371cb6e
nouveau: separate region_offset into map_handle and offset.
2007-07-12 10:46:57 +10:00
Arthur Huillet
5fbdf9da8b
fixed object creation code to not Oops on 64bits, worked around memalloc not working on 64bit for PCIGART
2007-07-12 02:35:39 +02:00
Arthur Huillet
b301a9051b
NV50 will not attempt to use PCIGART now
2007-07-11 15:01:37 +02:00
Arthur Huillet
d26ae22c2b
fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem
2007-07-11 14:56:27 +02:00
Ben Skeggs
5ccadac9e3
nouveau/nv50: G80 fixes.
...
Again, no hardware, so no idea if it'll even work yet. I understand how
the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)".
2007-07-11 14:22:59 +10:00
Ben Skeggs
13e1377044
nouveau: Some checks on userspace object handles.
2007-07-11 12:39:30 +10:00
Dave Airlie
2c9e05cf4c
Merge branch 'master' into cleanup
...
Conflicts:
libdrm/xf86drm.c
linux-core/drm_bo.c
linux-core/drm_fence.c
2007-07-11 11:23:41 +10:00
Arthur Huillet
694e1c5c3f
Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.
2007-07-11 02:35:10 +02:00
Ian Romanick
a9c49be6f8
Fix ioctl types.
...
I had moved code from xgi_drv.h to xgi_drm.h before changing the ioctl
types for XGI_IOCTL_(FB|PCIE)_ALLOC.
2007-07-09 18:52:43 -07:00
Ian Romanick
1f4e24b429
Move types shared with user mode to xgi_drm.h.
2007-07-09 16:33:14 -07:00
Ben Skeggs
023f7d9c00
nouveau: Allocate mappable VRAM for notifiers..
2007-07-09 23:58:00 +10:00
Ben Skeggs
31e33813e8
nouveau: Don't be so strict on <NV50
2007-07-09 20:02:14 +10:00
Ben Skeggs
3c58195ccd
nouveau: Avoid oops
...
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09 16:16:44 +10:00
Ben Skeggs
c806bba466
nouveau/nv50: Initial channel/object support
...
Should be OK on G84 for a single channel, multiple channels *almost* work.
Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs
3324342e42
nouveau: enable reporting for all PFIFO/PGRAPH irqs
2007-07-09 16:16:44 +10:00
Ben Skeggs
163f852612
nouveau: rewrite gpu object code
...
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.
Handle per-channel private instmem areas. This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?
Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Michel Dänzer
5b726b6390
radeon: Improve vblank counter.
...
The frame counter seems to increase only at the end of vertical blank, so we
need to add 1 while in vertical blank.
2007-07-06 09:50:50 +02:00
Michel Dänzer
91990946fa
One more spinlock initializer cleanup.
2007-07-03 12:33:51 +02:00
Ben Skeggs
e26ec51146
nouveau: small RAMFC cleanups
2007-06-29 14:20:50 +10:00
Ben Skeggs
1c32fecd6d
nouveau: Hack around possible Xv blit adaptor breakage
2007-06-28 21:01:17 +10:00
Ben Skeggs
2dd85772aa
nouveau/nv10: Fix earlier NV1x chips
...
Can't use nv04 code for them, since an extra field was inserted into
RAMFC after DMA_PUT/GET.
2007-06-28 04:23:17 +10:00
Ben Skeggs
68ecf61647
nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit
2007-06-28 03:26:44 +10:00
Ben Skeggs
18a6d1c9c3
nouveau: simplify PRAMIN access
2007-06-28 03:26:44 +10:00
Ben Skeggs
38617b6a26
nouveau: name some regs
2007-06-28 03:26:44 +10:00
Ben Skeggs
ce0d528d3c
nouveau/nv50: skeletal backend
2007-06-28 03:26:43 +10:00
Ben Skeggs
695599f18d
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
...
For various reasons, this ioctl was a bad idea.
At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.
However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers). Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs
4f2dd78ff3
nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks
2007-06-28 03:04:48 +10:00
Thomas Hellstrom
9b9a127ed0
More 64-bit padding.
2007-06-26 23:25:40 +02:00
Ian Romanick
5c27f8a70e
Add support SiS based XGI chips to SiS DRM.
2007-06-26 09:51:55 -07:00
Ben Skeggs
9f617522d9
nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303
2007-06-25 01:57:57 +10:00
Ben Skeggs
3dfc13e2da
nouveau: kill some dead code
2007-06-24 19:00:44 +10:00
Ben Skeggs
5f05cd7086
nouveau: NV04/NV10/NV20 PGRAPH engtab functions
...
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about
how they work to implement them sanely. The "old" context_switch() code
remains hooked up, so it shouldn't break anything.
NV20 will probably break if load_context() works. No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed. Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs
5d55b0655c
nouveau: NV3X PGRAPH engtab functions
2007-06-24 18:58:38 +10:00
Ben Skeggs
341bc78207
nouveau: NV1X/2X/3X PFIFO engtab functions
...
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs
05d86d950a
nouveau: NV04 PFIFO engtab functions
2007-06-24 18:57:09 +10:00
Ben Skeggs
acb710d1a5
nouveau: NV4X PGRAPH engtab functions
2007-06-24 18:56:40 +10:00
Ben Skeggs
f2e64d5276
nouveau: NV4X PFIFO engtab functions
2007-06-24 18:56:01 +10:00
Ben Skeggs
0afb3b518e
nouveau: split PFIFO/PGRAPH context creation
2007-06-24 18:55:23 +10:00
Ben Skeggs
9dbf322d26
nouveau: (mostly) hook up put_base again
2007-06-24 18:55:06 +10:00
Ben Skeggs
24b71c318a
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 18:54:51 +10:00
Ben Skeggs
5c7c07fd49
nouveau: rename engtab functions
2007-06-24 18:54:36 +10:00
Jesse Barnes
7f2a1cf275
Merge branch 'vblank-rework' into vblank
2007-06-22 11:12:02 -07:00
Jesse Barnes
97dcd7fd25
more vblank rework
...
- use a timer for disabling vblank events to avoid enable/disable calls too
often
- make i915 work with pre-965 chips again (would like to structure this
better, but this hack works on my test system)
2007-06-22 11:06:51 -07:00
Michel Dänzer
068ffc1e1b
radeon: Acknowledge all interrupts we're interested in.
...
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22 11:55:26 +02:00
Michel Dänzer
6e2cd7c163
drm_modeset_ctl_t fixes.
...
s/u64/drm_u64_t/ to allow userspace code using drm.h to compile.
Move 64 bit arg member to the beginning to avoid alignment issues with 32
bit userspace on 64 bit kernels.
2007-06-22 11:44:19 +02:00
Michel Dänzer
b8dd314875
Remove mask parameter from radeon_acknowledge_irqs().
...
Simply always acknowledge all interrupts we're interested in, to avoid hard
hangs when an unexpected interrupt is flagged.
2007-06-22 11:42:54 +02:00
Jesse Barnes
24c09faec1
Merge branch 'vblank-rework' into vblank
2007-06-21 15:26:34 -07:00
Jesse Barnes
afe842297f
RADEON: fix race in vblank interrupt handling
...
It's possible that we disable vblank interrupts and clear the
corresponding flag in irq_enable_reg, but receive an interrupt at just
the wrong time, causing us to not ack it properly, nor report to the
core kernel that it was handled. Fix that case by always handling
vblank interrupts, even if the irq_enable_reg field is clear.
2007-06-21 15:23:20 -07:00
Oliver McFadden
40f6a696cb
r300: Synchronized the register defines file; documentation changes.
2007-06-21 14:35:11 +00:00
Oliver McFadden
213732af43
r300: Allow writes to R300_VAP_PVS_WAITIDLE.
2007-06-21 14:32:58 +00:00
Jesse Barnes
2d24455ed8
Remove broken CRTC enable checks and incorrect user irq enable in set_pipe
...
routine.
2007-06-18 17:43:58 -07:00
Michel Dänzer
d8ed021d29
radeon: VBlank rework fixups.
...
Fix range of frame counter registers.
Use DRM_ERR() instead of Linux specific error codes in shared code.
Remove duplicate register definitions and superfluous local variables.
2007-06-18 13:10:37 +02:00
Oliver McFadden
215787e429
r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1.
2007-06-18 08:42:46 +00:00
Oliver McFadden
8038e7b60f
r300: Synchronized the register defines file again.
2007-06-18 08:36:50 +00:00
Jesse Barnes
741d1c8031
Remove broken crtc enable checks, radeon does it slightly differently
...
(this makes get_vblank_counter return an actual value).
2007-06-15 17:06:46 -07:00
Jesse Barnes
b6610363e3
First cut at radeon support for the vblank rework.
2007-06-15 11:21:57 -07:00
Michel Dänzer
3d5d41fa98
i915: Fix handling of breadcrumb counter wraparounds.
2007-06-15 17:13:11 +02:00
Michel Dänzer
82e2c3304d
Wake up vblank waitqueue in drm_handle_vblank().
2007-06-15 10:25:50 +02:00
Michel Dänzer
914a810a82
i915: Fix tests for vblank interrupts being enabled on CRTC by X server.
2007-06-15 10:21:44 +02:00
Michel Dänzer
1000d88ddf
Fix memory leaks in vblank error paths.
...
Also use drm_calloc instead of drm_alloc and memset, and use the size of the
struct instead of the size of the pointer for allocation...
2007-06-15 10:10:33 +02:00
Jesse Barnes
b06268294a
Comment new vblank routines and fixup several issues:
...
- use correct refcount variable in get/put routines
- extract counter update from drm_vblank_get
- make signal handling callback per-crtc
- update interrupt handling logic, drivers should use drm_handle_vblank
- move wakeup and counter update logic to new drm_handle_vblank routine
- fixup usage of get/put in light of counter update extraction
- fix longstanding bug in signal code, update pending counter only
*after* we're sure we'll setup signal handling
2007-06-14 11:32:31 -07:00
Jesse Barnes
1a4b9294a2
Remove unnecessary (and uncommented!) read barrier from the interrupt
...
path. It doesn't appear to serve any useful purpose.
2007-06-12 16:29:09 -07:00
Jesse Barnes
ca47fa90b7
Update vblank code:
...
- move pre/post modeset ioctl to core
- fixup i915 buffer swap
- fix outstanding signal count code
- create new core vblank init routine
- test (works with glxgears)
- simplify i915 interrupt handler
2007-06-12 13:35:41 -07:00
Jesse Barnes
db689c7b95
Initial checkin of vblank rework. Code attempts to reduce the number
...
of vblank interrupt in order to save power.
2007-06-12 10:44:21 -07:00
Thomas Hellstrom
f984b1b8d1
Fix some obvious bugs.
2007-06-12 12:30:33 +02:00
Thomas Hellstrom
b6b5df24b9
Try to make buffer object / fence object ioctl args 64-bit safe.
...
Introduce tile members for future tiled buffer support.
Allow user-space to explicitly define a fence-class.
Remove the implicit fence-class mechanism.
64-bit wide buffer object flag member.
2007-06-12 12:21:38 +02:00
Oliver McFadden
3181573073
r300: Added the CP maximum fetch size and ring rptr update variables.
2007-06-08 19:40:57 +00:00
Oliver McFadden
39625f9621
r300: Small correction to the previous commit.
2007-06-05 19:19:42 +00:00
Alex Deucher
9e0bd88c61
r300: Document more of the RADEON_RBBM_STATUS register.
2007-06-05 19:05:49 +00:00
Wang Zhenyu
109e2a10f2
Add support for the G33, Q33, and Q35 chipsets.
...
These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory. So, we have the X Server allocate that memory and tell
us the address, instead.
2007-06-05 11:15:29 -07:00
Maurice van der Pot
4327d7f314
nouveau: fix RAMHT wrapping
2007-06-04 10:49:30 +10:00
Dave Airlie
a05d4fecd3
radeon: refine irq acking for vbl on crtc 2
2007-06-03 18:30:52 +10:00
root
8d95f4bd91
Revert "move i915 to new drm_wait_on function"
...
This reverts commit feb6803778
.
This was a bad idea, the macro is actually a bit harder to convert
to a static for the other use cases
2007-06-03 18:11:44 +10:00
Dave Airlie
4e9d215bdf
radeon: add support for vblank on crtc2
...
This add support for CRTC2 vblank on radeon similiar to the i915 support
2007-06-03 16:28:21 +10:00
Wang Zhenyu
5c394b309d
i915: Add support for 945GME chip
2007-05-31 11:09:15 +01:00
Wang Zhenyu
3917f85c73
i915: Add support for 965GME/GLE chip.
2007-05-31 11:09:07 +01:00
Jung-uk Kim
b0c8d885ce
Update a bunch of FreeBSD port code.
...
Tested on r200/r300. i915 updates still remain to be done.
2007-05-29 15:02:44 -07:00
Thomas Gleixner
2bb7703698
drm: spinlock initializer cleanup
2007-05-26 05:20:59 +10:00
Dave Airlie
ad02c536df
radeon: add other IGP chipsets
2007-05-26 04:02:55 +10:00
Dave Airlie
58b2ed7832
Revert "drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls."
...
This reverts commit 3fdef0dc20
.
ditto not on master yet
2007-05-26 03:48:08 +10:00
Dave Airlie
375f3f2884
Revert "drm/ttm: cleanup most of fence ioctl split out"
...
This reverts commit 3dfc1400e9
.
this shouldn't have gone on master yet
2007-05-26 03:47:48 +10:00
Dave Airlie
ce58e53a01
whitespace fixups from kernel
2007-05-26 03:32:34 +10:00
Dave Airlie
3dfc1400e9
drm/ttm: cleanup most of fence ioctl split out
2007-05-26 03:32:34 +10:00
Dave Airlie
3fdef0dc20
drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls.
...
This is the first bunch of ioctls
2007-05-26 03:32:34 +10:00
Dave Airlie
7b48f0022a
drm: cleanup use of Linux list handling macros
...
This makes the drms use of the list handling macros a lot cleaner
and more along the lines of how they should be used.
2007-05-26 04:26:24 +10:00
Oliver McFadden
ca725bba84
r300: Added my comments into r300_reg.h.
2007-05-13 16:18:54 +00:00
Oliver McFadden
c6ff0caaa3
r300: Synchronized R300 register defines file.
...
Just moved the indent control comments so that indent doesn't try to change
anything.
2007-05-13 07:53:57 +00:00
Matthieu Castet
e9b604ed3f
nouveau : nv10 graph move clipping value to per channel init
2007-05-12 15:36:48 +02:00
Matthieu Castet
5d623935c0
nouveau : nv10 graph clipping values were forgoten in ddx to drm commit
2007-05-12 15:36:48 +02:00
Keith Packard
e4d163d81a
Allow vblank interrupts to remain disabled across VT switch.
...
i915_driver_irq_postinstall was forcing vblank interrupts to pipe A when
called with vblank interrupts disabled. This caused vblank interrupts to be
accidentally re-enabled when VT switching the X server. Instead, start the
driver with vblank interrupts enabled on pipe A to support older X servers,
but then leave control over the state to the X server if it is able to do so.
2007-05-10 13:15:32 -07:00
Oliver McFadden
e0056c7eb4
r300: Synchronized R300 register defines file.
2007-05-09 18:31:31 +00:00
Oliver McFadden
a02b045142
r300: Synchronized R300 register defines file.
2007-05-09 15:22:40 +00:00
Matthieu Castet
59784116bf
nouveau : fix fifo context size for nv10
2007-05-08 21:20:25 +02:00
Dave Airlie
b2a875ba89
ttm: complete drm buffer object ioctl split
...
retain the op operation for validate/fence operations
2007-05-08 18:25:15 +10:00
Dave Airlie
25c51f539f
drm/ttm: ioctl cleanup for buffer object - user side only
...
This just cleans up the xf86drm.c to what I want and drm.h,
I need to fix up the kernel internals to suit these changes now.
I've moved to using struct instead of typedefs for the bo and it doesn't look
that bad so I'll do the same thing for mm and fence..
2007-05-08 17:53:58 +10:00
Oliver McFadden
4e858f8811
r300: Synchronize the register file from Mesa.
2007-05-06 12:47:03 +00:00
Oliver McFadden
87ec1fea6c
r300: Use the defined names for known registers.
2007-05-06 12:35:16 +00:00
Dave Airlie
6a62941eca
drm/ttm: cleanup most of fence ioctl split out
2007-05-06 11:35:11 +10:00
Dave Airlie
ee8954cb53
drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls.
...
This is the first bunch of ioctls
2007-05-06 11:17:30 +10:00
Michel Dänzer
f06ad82ecd
Fix userspace ABI breakage from 3c384a9ad5
.
2007-05-01 17:03:55 +02:00
Michel Dänzer
ca1cd3257c
radeon: Don't mess up page flipping when a file descriptor is closed.
...
There can still be other contexts that may use page flipping later on, so don't
just unilaterally 'clean it up', which could lead to the wrong page being
displayed, e.g. when running 3D apps with a GLX compositing manager such as
compiz using page flipping.
2007-04-29 12:37:51 +02:00
Dave Airlie
feb6803778
move i915 to new drm_wait_on function
2007-04-28 15:07:43 +10:00
Dave Airlie
9f9c19065c
remove DRM_GETSAREA and replace with drm_getsarea function
2007-04-28 15:07:43 +10:00
George Sapountzis
e88934274a
Revert "bug 7092 : add pci ids for mach64 in Dell poweredge 4200"
...
This reverts commit 255f3e6f76
.
Rage IIc does not have a vertex setup engine.
2007-04-26 14:16:51 +03:00
George Sapountzis
942d9be296
freebsd: remove stray apperance of IN_MODULE.
...
The xserver no longer uses the libc-wrapper.
2007-04-26 14:16:13 +03:00
Jesse Barnes
3c384a9ad5
Add new buffer object type for kernel allocations that don't initially have a user mapping.
...
(cherry picked from commit 2e21779992
)
2007-04-26 16:04:09 +10:00
Stephane Marchesin
61477d60c4
nouveau: fix wacky pci id
2007-04-23 22:37:36 +02:00
Thomas Hellstrom
e805ca959d
via: Make sure we flush write-combining using a follow-up read.
2007-04-17 08:58:23 +02:00
Matthieu Castet
9b7211dd67
nouveau: nv10 per channel init from ddx
2007-04-10 23:20:13 +02:00
Oliver McFadden
059b5d9077
rs480: Renamed some unknown registers. See dri-devel list.
2007-04-09 23:23:40 +00:00
Ben Skeggs
2d7f9f59c3
nouveau: NV46 support
2007-04-09 23:20:26 +10:00
Dave Airlie
29f8fe8046
radeon: bump version for IGPGART support
2007-04-09 22:00:34 +10:00
Dave Airlie
a70f8e0ab2
radeon: add support for reverse engineered xpress200m
...
The IGPGART setup code was traced using mmio-trace on fglrx by myself
and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel.
This code doesn't let the 3D driver work properly as the card has no
vertex shader support.
Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this
work on.
2007-04-09 21:52:59 +10:00
Dave Airlie
46257c51c1
i915: use breadcrumb macro everywhere
2007-04-06 20:21:44 +10:00
Ben Skeggs
78034c06df
nouveau: make a note about a bit that breaks some cards
2007-04-06 03:27:55 +10:00
Ben Skeggs
38f52402a8
nouveau: Power up all card units by default on startup.
2007-04-06 03:26:19 +10:00
Thomas Hellstrom
139e4bbc73
Make sure we ack irqs before we read a breadcrumb so that
...
breadcrumb updates that occur _AFTER_ we've read the breadcrumb really
generates a new IRQ.
2007-04-03 10:29:15 +02:00
Oliver McFadden
5395a92d40
r300: Synchronize the register header file again.
...
It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
2007-04-02 19:45:10 +00:00
Matthieu Castet
cbbdbd5e65
nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+
...
http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file.
Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e , NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
2007-04-01 14:31:41 +02:00
Matthieu Castet
25cedcf76f
nouveau : nv10 ctx switch fix
...
restoring NV10_PGRAPH_CTX_SWITCH1 now works
2007-04-01 14:21:29 +02:00
Matthieu Castet
223061e084
nouveau : set the correct PGRAPH_CTX_CONTROL register
...
"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-04-01 00:44:11 +02:00
Eric Anholt
ddb1715e06
Merge branch 'crestline-qa', adding support for the 965GM chipset.
2007-03-30 13:11:39 -07:00
Stephane Marchesin
bdabc8f998
nouveau: fix nv04 context switches.
2007-03-29 00:54:18 +02:00
Dave Airlie
81b811da37
drm/i915: set the bo up at firstopen time not after DMA init
...
This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
Nian Wu
406a894e52
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-27 12:53:13 +08:00
Ben Skeggs
674cefd4fe
nouveau: move card initialisation into the drm
...
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
Nian Wu
e7cd5a1e2d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-23 17:00:41 +08:00
Ben Skeggs
4988fa4886
nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
2007-03-23 15:25:37 +11:00
Ben Skeggs
2bb9de96d5
nouveau: remove unused cruft
2007-03-23 13:45:29 +11:00
Nian Wu
0467ad4118
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-21 17:00:43 +08:00
Ben Skeggs
e22225416a
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 17:57:47 +11:00
Nian Wu
8398b99d8d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-19 17:00:31 +08:00
Dave Airlie
26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
Dave Airlie
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
Nian Wu
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
Oliver McFadden
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
...
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
Nian Wu
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
Oliver McFadden
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
...
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
Ben Skeggs
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
Ben Skeggs
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
Ben Skeggs
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
Oliver McFadden
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
...
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
Oliver McFadden
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
Nian Wu
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
Patrice Mandin
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
Nian Wu
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
Thomas Hellstrom
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
Nian Wu
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
Dave Airlie
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
...
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
Dave Airlie
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
...
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
Nian Wu
6c48b8e7ff
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-01 09:02:09 -05:00
Ben Skeggs
72caa48c82
nouveau: intrusive drm interface changes
...
graphics objects:
- No longer takes flags/dmaobj parameters, requires some major changes
to the ddx to setup the object through the FIFO. This change is
likely to cause breakages on some cards (tested on NV05,NV28,NV35,
NV40 and NV4E).
dma objects:
- now takes a "class" parameter, not really used yet but we may need
it at some point.
- parameters are checked, so clients can't randomly create DMA objects
pointing at whatever they feel like.
misc:
- Added FB_SIZE/AGP_SIZE getparams
- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Nian Wu
df2fc3ec62
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-02-25 17:06:13 -08:00
Jakob Bornecrantz
9d8ba2d0d4
drm: remove unnecessary NULL checks, and fix some indents..
2007-02-25 10:48:26 +11:00
Thomas Hellstrom
e0f53e59be
Simple fence object sample driver for via, based on idling the GPU.
...
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
Thomas Hellstrom
7766378d97
Initial support for fence object classes.
...
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
Thomas Hellstrom
a78f70faad
Merge branch 'ttm-vram-0-1-branch'
2007-02-14 15:33:40 +01:00
Thomas Hellstrom
5c9a7b0f94
Remove an intel-specific hack and replace it with a fence driver callback.
2007-02-14 13:31:35 +01:00
Stephane Marchesin
f524870184
nouveau: fix the build on big endian (thanks CyberFoxx)
2007-02-14 00:08:55 +01:00
B. Rathmann
59af900e4f
nouveau: fix memory initialization with multiple cards.
2007-02-14 00:07:31 +01:00
Thomas Hellstrom
e1460426b8
Bugzilla Bug #9457
...
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.
Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.
It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
Wang Zhenyu
80095ffe01
i915: Add 965GM pci id update
2007-02-13 16:20:45 +08:00
Thomas Hellstrom
abc14ddfb5
Update flags and comments.
2007-02-12 21:40:42 +01:00
Aapo Tahkola
130c39be3c
Sync r300_reg.h from mesa driver. #10210
2007-02-11 10:24:14 +02:00
Michel Dänzer
4f795a05f1
Merge branch 'i915-pageflip'
2007-03-10 00:11:10 +01:00
Michel Dänzer
d734992e6a
i915: Only wait for pending flips before asynchronous flips again.
2007-03-10 00:10:49 +01:00
Michel Dänzer
0741064df4
i915: Do not wait for pending flips on both pipes at the same time.
...
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
Ben Skeggs
1b3a6d4775
nouveau: remove a hack that's not needed since the last interface change.
2007-03-07 21:17:45 +11:00
Ben Skeggs
5bd0e52dba
nouveau: ack PFIFO interrupts at PFIFO, not PMC.
2007-03-07 21:00:55 +11:00
Michel Dänzer
a33859184a
i915: Eliminate dev_priv->current_page.
...
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
Michel Dänzer
074e10b384
i915: Only clean up page flipping when the last client goes away, not any one.
2007-02-28 15:57:08 +01:00
Michel Dänzer
1cdc1b6fba
i915: Don't emit waits for pending flips before emitting synchronous flips.
...
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.
Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
Michel Dänzer
fd0fed3f1e
i915: Fix test for synchronous flip affecting both pipes.
2007-02-28 12:33:56 +01:00
Michel Dänzer
1a0d890a42
i915: Add support for scheduled buffer swaps to be done as flips.
...
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
Michel Dänzer
5a40c043cc
Add DRM_VBLANK_FLIP.
...
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
Michel Dänzer
6f89584e13
i915: Improved page flipping support, including triple buffering.
...
Pages are tracked independently on each pipe.
Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
Michel Dänzer
34aa3393d0
i915: Page flipping enhancements.
...
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.
Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
Michel Dänzer
078e430726
i915: Unify breadcrumb emission.
2007-02-19 15:08:40 +01:00
Thomas Hellstrom
53aee3122a
I915 accelerated blit copy functional.
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Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
Eric Anholt
898aca1a66
Warning fix: correct type of i915_mmio argument.
2007-02-07 21:26:02 -08:00
Eric Anholt
ef9a9d3cd1
Define __iomem for systems without it.
2007-02-07 21:26:01 -08:00
Eric Anholt
8918748058
Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.
2007-02-07 21:26:01 -08:00
Thomas Hellstrom
c1fbd8a566
Checkpoint commit.
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Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
Thomas Hellstrom
609e3b0375
Implement a policy for selecting memory types.
2007-02-06 14:20:33 +01:00
Stephane Marchesin
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
Stephane Marchesin
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
Stephane Marchesin
0c13657c33
nouveau: plugin the nv04 graph init function.
2007-02-03 06:00:29 +01:00
Stephane Marchesin
7ab9e7f36f
nouveau: cleanup the nv04 pgraph save/restore mechanism.
2007-02-03 05:56:42 +01:00
Stephane Marchesin
d69902db3b
nouveau: fix nv04 graph routines for new register names.
2007-02-03 05:25:36 +01:00
Stephane Marchesin
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
Stephane Marchesin
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
Matthieu Castet
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
Matthieu Castet
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
Thomas Hellstrom
6c04185857
via: Try to improve command-buffer chaining.
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Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
Thomas Hellstrom
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
Thomas Hellstrom
3024f23c65
memory manager: Make device driver aware of different memory types.
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Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00