18a6d1c9c3
nouveau: simplify PRAMIN access
2007-06-28 03:26:44 +10:00
38617b6a26
nouveau: name some regs
2007-06-28 03:26:44 +10:00
ce0d528d3c
nouveau/nv50: skeletal backend
2007-06-28 03:26:43 +10:00
695599f18d
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
...
For various reasons, this ioctl was a bad idea.
At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.
However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers). Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
4f2dd78ff3
nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks
2007-06-28 03:04:48 +10:00
9b9a127ed0
More 64-bit padding.
2007-06-26 23:25:40 +02:00
5c27f8a70e
Add support SiS based XGI chips to SiS DRM.
2007-06-26 09:51:55 -07:00
9f617522d9
nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303
2007-06-25 01:57:57 +10:00
3dfc13e2da
nouveau: kill some dead code
2007-06-24 19:00:44 +10:00
5f05cd7086
nouveau: NV04/NV10/NV20 PGRAPH engtab functions
...
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about
how they work to implement them sanely. The "old" context_switch() code
remains hooked up, so it shouldn't break anything.
NV20 will probably break if load_context() works. No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed. Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
5d55b0655c
nouveau: NV3X PGRAPH engtab functions
2007-06-24 18:58:38 +10:00
341bc78207
nouveau: NV1X/2X/3X PFIFO engtab functions
...
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
05d86d950a
nouveau: NV04 PFIFO engtab functions
2007-06-24 18:57:09 +10:00
acb710d1a5
nouveau: NV4X PGRAPH engtab functions
2007-06-24 18:56:40 +10:00
f2e64d5276
nouveau: NV4X PFIFO engtab functions
2007-06-24 18:56:01 +10:00
0afb3b518e
nouveau: split PFIFO/PGRAPH context creation
2007-06-24 18:55:23 +10:00
9dbf322d26
nouveau: (mostly) hook up put_base again
2007-06-24 18:55:06 +10:00
24b71c318a
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 18:54:51 +10:00
5c7c07fd49
nouveau: rename engtab functions
2007-06-24 18:54:36 +10:00
7f2a1cf275
Merge branch 'vblank-rework' into vblank
2007-06-22 11:12:02 -07:00
97dcd7fd25
more vblank rework
...
- use a timer for disabling vblank events to avoid enable/disable calls too
often
- make i915 work with pre-965 chips again (would like to structure this
better, but this hack works on my test system)
2007-06-22 11:06:51 -07:00
068ffc1e1b
radeon: Acknowledge all interrupts we're interested in.
...
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22 11:55:26 +02:00
6e2cd7c163
drm_modeset_ctl_t fixes.
...
s/u64/drm_u64_t/ to allow userspace code using drm.h to compile.
Move 64 bit arg member to the beginning to avoid alignment issues with 32
bit userspace on 64 bit kernels.
2007-06-22 11:44:19 +02:00
b8dd314875
Remove mask parameter from radeon_acknowledge_irqs().
...
Simply always acknowledge all interrupts we're interested in, to avoid hard
hangs when an unexpected interrupt is flagged.
2007-06-22 11:42:54 +02:00
24c09faec1
Merge branch 'vblank-rework' into vblank
2007-06-21 15:26:34 -07:00
afe842297f
RADEON: fix race in vblank interrupt handling
...
It's possible that we disable vblank interrupts and clear the
corresponding flag in irq_enable_reg, but receive an interrupt at just
the wrong time, causing us to not ack it properly, nor report to the
core kernel that it was handled. Fix that case by always handling
vblank interrupts, even if the irq_enable_reg field is clear.
2007-06-21 15:23:20 -07:00
40f6a696cb
r300: Synchronized the register defines file; documentation changes.
2007-06-21 14:35:11 +00:00
213732af43
r300: Allow writes to R300_VAP_PVS_WAITIDLE.
2007-06-21 14:32:58 +00:00
2d24455ed8
Remove broken CRTC enable checks and incorrect user irq enable in set_pipe
...
routine.
2007-06-18 17:43:58 -07:00
d8ed021d29
radeon: VBlank rework fixups.
...
Fix range of frame counter registers.
Use DRM_ERR() instead of Linux specific error codes in shared code.
Remove duplicate register definitions and superfluous local variables.
2007-06-18 13:10:37 +02:00
215787e429
r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1.
2007-06-18 08:42:46 +00:00
8038e7b60f
r300: Synchronized the register defines file again.
2007-06-18 08:36:50 +00:00
741d1c8031
Remove broken crtc enable checks, radeon does it slightly differently
...
(this makes get_vblank_counter return an actual value).
2007-06-15 17:06:46 -07:00
b6610363e3
First cut at radeon support for the vblank rework.
2007-06-15 11:21:57 -07:00
3d5d41fa98
i915: Fix handling of breadcrumb counter wraparounds.
2007-06-15 17:13:11 +02:00
82e2c3304d
Wake up vblank waitqueue in drm_handle_vblank().
2007-06-15 10:25:50 +02:00
914a810a82
i915: Fix tests for vblank interrupts being enabled on CRTC by X server.
2007-06-15 10:21:44 +02:00
1000d88ddf
Fix memory leaks in vblank error paths.
...
Also use drm_calloc instead of drm_alloc and memset, and use the size of the
struct instead of the size of the pointer for allocation...
2007-06-15 10:10:33 +02:00
b06268294a
Comment new vblank routines and fixup several issues:
...
- use correct refcount variable in get/put routines
- extract counter update from drm_vblank_get
- make signal handling callback per-crtc
- update interrupt handling logic, drivers should use drm_handle_vblank
- move wakeup and counter update logic to new drm_handle_vblank routine
- fixup usage of get/put in light of counter update extraction
- fix longstanding bug in signal code, update pending counter only
*after* we're sure we'll setup signal handling
2007-06-14 11:32:31 -07:00
1a4b9294a2
Remove unnecessary (and uncommented!) read barrier from the interrupt
...
path. It doesn't appear to serve any useful purpose.
2007-06-12 16:29:09 -07:00
ca47fa90b7
Update vblank code:
...
- move pre/post modeset ioctl to core
- fixup i915 buffer swap
- fix outstanding signal count code
- create new core vblank init routine
- test (works with glxgears)
- simplify i915 interrupt handler
2007-06-12 13:35:41 -07:00
db689c7b95
Initial checkin of vblank rework. Code attempts to reduce the number
...
of vblank interrupt in order to save power.
2007-06-12 10:44:21 -07:00
f984b1b8d1
Fix some obvious bugs.
2007-06-12 12:30:33 +02:00
b6b5df24b9
Try to make buffer object / fence object ioctl args 64-bit safe.
...
Introduce tile members for future tiled buffer support.
Allow user-space to explicitly define a fence-class.
Remove the implicit fence-class mechanism.
64-bit wide buffer object flag member.
2007-06-12 12:21:38 +02:00
3181573073
r300: Added the CP maximum fetch size and ring rptr update variables.
2007-06-08 19:40:57 +00:00
39625f9621
r300: Small correction to the previous commit.
2007-06-05 19:19:42 +00:00
9e0bd88c61
r300: Document more of the RADEON_RBBM_STATUS register.
2007-06-05 19:05:49 +00:00
109e2a10f2
Add support for the G33, Q33, and Q35 chipsets.
...
These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory. So, we have the X Server allocate that memory and tell
us the address, instead.
2007-06-05 11:15:29 -07:00
c9dbe0f2c2
invalidate gart tlb on PCIE after table change
2007-06-05 12:38:43 +10:00
4294dcc050
complete PCIE backend for ttm
...
ttm test runs with it at least, needs to do more testing on it
2007-06-05 12:26:06 +10:00
07345af838
Merge branch 'origin' into radeon-ttm
...
Conflicts:
shared-core/radeon_drv.h
2007-06-05 10:09:11 +10:00
4327d7f314
nouveau: fix RAMHT wrapping
2007-06-04 10:49:30 +10:00
a05d4fecd3
radeon: refine irq acking for vbl on crtc 2
2007-06-03 18:30:52 +10:00
8d95f4bd91
Revert "move i915 to new drm_wait_on function"
...
This reverts commit feb6803778
2007-06-03 18:11:44 +10:00
4e9d215bdf
radeon: add support for vblank on crtc2
...
This add support for CRTC2 vblank on radeon similiar to the i915 support
2007-06-03 16:28:21 +10:00
5c394b309d
i915: Add support for 945GME chip
2007-05-31 11:09:15 +01:00
3917f85c73
i915: Add support for 965GME/GLE chip.
2007-05-31 11:09:07 +01:00
b0c8d885ce
Update a bunch of FreeBSD port code.
...
Tested on r200/r300. i915 updates still remain to be done.
2007-05-29 15:02:44 -07:00
2bb7703698
drm: spinlock initializer cleanup
2007-05-26 05:20:59 +10:00
ad02c536df
radeon: add other IGP chipsets
2007-05-26 04:02:55 +10:00
58b2ed7832
Revert "drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls."
...
This reverts commit 3fdef0dc20
2007-05-26 03:48:08 +10:00
375f3f2884
Revert "drm/ttm: cleanup most of fence ioctl split out"
...
This reverts commit 3dfc1400e9
2007-05-26 03:47:48 +10:00
ce58e53a01
whitespace fixups from kernel
2007-05-26 03:32:34 +10:00
3dfc1400e9
drm/ttm: cleanup most of fence ioctl split out
2007-05-26 03:32:34 +10:00
3fdef0dc20
drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls.
...
This is the first bunch of ioctls
2007-05-26 03:32:34 +10:00
7b48f0022a
drm: cleanup use of Linux list handling macros
...
This makes the drms use of the list handling macros a lot cleaner
and more along the lines of how they should be used.
2007-05-26 04:26:24 +10:00
462d5a0dfc
Suspend/resume support (incomplete).
2007-05-22 17:49:04 -07:00
e918d2b781
Call preallocated space VRAM instead of PRIV0 to be more consistent with
...
other drivers.
2007-05-22 13:38:58 -07:00
3851600b34
Fix merge problem.
2007-05-18 13:59:46 +01:00
315cf14af8
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into modesetting-101
...
Conflicts:
shared-core/i915_dma.c
2007-05-18 13:48:56 +01:00
b7bf317f42
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
...
Conflicts:
linux-core/drm_crtc.c
linux-core/drm_fb.c
Lots of changes to merge with alanh's latest stuff:
o fix use of fb->pitch now that it has the right value
o add new helper for finding the CRTC given an FB
o fix new fb_probe/fb_remove functions to take a CRTC
o fixup callers of new FB routines
o port drm_fb changes to intel_fb
o check for errors after creating fb buffer object
o go back to using cfb_imageblit since the accel stubs aren't ready
2007-05-17 10:35:07 -07:00
a18b4befb9
Fix FB pitch value (we had it wrong and were working around it in a few
...
places).
Add new FB hooks to the drm driver structure and make i915 use them for an
Intel specific FB driver. This will allow acceleration and better handling
of the command stream.
2007-05-17 09:00:06 -07:00
ca725bba84
r300: Added my comments into r300_reg.h.
2007-05-13 16:18:54 +00:00
c6ff0caaa3
r300: Synchronized R300 register defines file.
...
Just moved the indent control comments so that indent doesn't try to change
anything.
2007-05-13 07:53:57 +00:00
e9b604ed3f
nouveau : nv10 graph move clipping value to per channel init
2007-05-12 15:36:48 +02:00
5d623935c0
nouveau : nv10 graph clipping values were forgoten in ddx to drm commit
2007-05-12 15:36:48 +02:00
e4d163d81a
Allow vblank interrupts to remain disabled across VT switch.
...
i915_driver_irq_postinstall was forcing vblank interrupts to pipe A when
called with vblank interrupts disabled. This caused vblank interrupts to be
accidentally re-enabled when VT switching the X server. Instead, start the
driver with vblank interrupts enabled on pipe A to support older X servers,
but then leave control over the state to the X server if it is able to do so.
2007-05-10 13:15:32 -07:00
eba00df120
Just some minor cleanups.
2007-05-10 13:16:05 +01:00
e0056c7eb4
r300: Synchronized R300 register defines file.
2007-05-09 18:31:31 +00:00
a02b045142
r300: Synchronized R300 register defines file.
2007-05-09 15:22:40 +00:00
59784116bf
nouveau : fix fifo context size for nv10
2007-05-08 21:20:25 +02:00
b2a875ba89
ttm: complete drm buffer object ioctl split
...
retain the op operation for validate/fence operations
2007-05-08 18:25:15 +10:00
25c51f539f
drm/ttm: ioctl cleanup for buffer object - user side only
...
This just cleans up the xf86drm.c to what I want and drm.h,
I need to fix up the kernel internals to suit these changes now.
I've moved to using struct instead of typedefs for the bo and it doesn't look
that bad so I'll do the same thing for mm and fence..
2007-05-08 17:53:58 +10:00
4e858f8811
r300: Synchronize the register file from Mesa.
2007-05-06 12:47:03 +00:00
87ec1fea6c
r300: Use the defined names for known registers.
2007-05-06 12:35:16 +00:00
6a62941eca
drm/ttm: cleanup most of fence ioctl split out
2007-05-06 11:35:11 +10:00
ee8954cb53
drm/ttm: cleanup mm_ioctl ioctls to be separate ioctls.
...
This is the first bunch of ioctls
2007-05-06 11:17:30 +10:00
f06ad82ecd
Fix userspace ABI breakage from 3c384a9ad5.
2007-05-01 17:03:55 +02:00
89231953d1
Add support for user defined modes
...
This allows userspace to specify modes and add them to the modesetting
system and attach modes to outputs
2007-05-01 13:16:29 +10:00
ca1cd3257c
radeon: Don't mess up page flipping when a file descriptor is closed.
...
There can still be other contexts that may use page flipping later on, so don't
just unilaterally 'clean it up', which could lead to the wrong page being
displayed, e.g. when running 3D apps with a GLX compositing manager such as
compiz using page flipping.
2007-04-29 12:37:51 +02:00
feb6803778
move i915 to new drm_wait_on function
2007-04-28 15:07:43 +10:00
9f9c19065c
remove DRM_GETSAREA and replace with drm_getsarea function
2007-04-28 15:07:43 +10:00
e88934274a
Revert "bug 7092 : add pci ids for mach64 in Dell poweredge 4200"
...
This reverts commit 255f3e6f76
2007-04-26 14:16:51 +03:00
942d9be296
freebsd: remove stray apperance of IN_MODULE.
...
The xserver no longer uses the libc-wrapper.
2007-04-26 14:16:13 +03:00
3c384a9ad5
Add new buffer object type for kernel allocations that don't initially have a user mapping.
...
(cherry picked from commit 2e21779992
2007-04-26 16:04:09 +10:00
b589b846e7
Merge branch 'origin' into modesetting-101
2007-04-26 15:56:21 +10:00
34be91fe4e
i915: fix vblank pipe setup
2007-04-26 14:50:00 +10:00
61477d60c4
nouveau: fix wacky pci id
2007-04-23 22:37:36 +02:00
0f3c5148f0
fixup vrefresh reporting, it should now be *1000 in userspace
2007-04-23 09:10:46 +10:00
eb892fb09d
Add a monitor information structure separate from the EDID data for tracking
...
monitor limits, etc.
2007-04-20 17:59:30 -07:00
e46e028bd2
Merge branch 'origin' into modesetting-101
...
Conflicts:
linux-core/drm_bo.c
Merge in changes from master from Thomas fixiing TTM problems
2007-04-18 14:11:49 +10:00
7c9e19ba55
clean up ring buffer and TTM in i915_driver_unload
...
I've commented out the framebuffer for now
2007-04-18 10:39:27 +10:00
1c7f895fa6
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
...
Conflicts:
shared-core/i915_init.c - reconcile with airlied's new code
2007-04-17 10:14:18 -07:00
4e4d9cbeb3
Move initial framebuffer allocation and configuration to drm_initial_config,
...
remove i915_driver_load fb related stuff. Add a small helper for setting up
outputs.
2007-04-17 10:00:37 -07:00
eeb5de0594
Cleanup whitespace, rename macro argument.
2007-04-17 09:59:21 -07:00
32b5616cc6
Correct PCI ID for i845
2007-04-17 16:08:26 +01:00
79aa1d5474
another large overhaul of interactions with userspace...
...
We need to keep a list of user created fbs to nuke on master exit.
We also need to use the bo properly.
2007-04-17 18:16:38 +10:00
e805ca959d
via: Make sure we flush write-combining using a follow-up read.
2007-04-17 08:58:23 +02:00
65619cab27
Fix PRIV0 memory initialization (mm_init takes pages, not bytes), align fb
...
allocation correctly, and use drm_mem_reg_iomap to map ring buffer object.
2007-04-14 15:35:21 -07:00
cc471a361f
i915/drm: clean up a lot of the i915/drm startup/teardown sequences
...
When the kernel driver is loaded it sets up a lot of stuff..
it tears down the same stuff on unload.
This add a new map type called DRM_DRIVER which means the driver will clean the mapping up
and fix up the map cleaner
2007-04-13 14:51:16 +10:00
e183a091ff
Initialize the hw lock waitqueue so we don't hang in drm_lastclose.
2007-04-12 11:40:12 -07:00
2160e267ff
Don't use drm_setup, do SAREA allocation and mapping directly instead.
2007-04-12 09:01:53 -07:00
e7b97f5523
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
2007-04-12 08:55:51 -07:00
9420ab4b41
Merge remote branch 'origin/modesetting-101' into modesetting-101
2007-04-12 15:10:08 +01:00
e8bd9fdf31
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
2007-04-11 20:41:54 -07:00
0430a80fc7
Remove debug statement about buffer objects
2007-04-11 20:41:27 -07:00
fb6c5aacb9
only initialise modes when fbcon or fbset asks for it
2007-04-12 11:54:49 +10:00
a81558d8b3
add getfb ioctl
2007-04-12 08:45:40 +10:00
9d7160c43a
Use new kernel buffer object type and cleanup agp probing.
2007-04-11 12:52:57 -07:00
2e21779992
Add new buffer object type for kernel allocations that don't initially have a user mapping.
2007-04-11 12:51:52 -07:00
8dd75bd601
Add aperture size and preallocation probing (from intelfb), cleanup load code to be more general.
2007-04-11 11:47:58 -07:00
cc7faa4de8
fix modeset cleanup for LVDS and reenable it in i915.
2007-04-11 07:21:24 -07:00
78598fdaa8
Various changes for in-kernel modesetting:
...
- allow drm_buffer_object_create to be called w/o dev_mapping
- fixup i915 init code to allocate memory, fb and set modes right
- pass fb to drm_initial_config for setup
- change some debug output to make it easier to spot
- fixup lvds code to use DDC probing correctly
2007-04-11 07:07:54 -07:00
a6cc6a778f
add support for setting a framebuffer depth
2007-04-11 17:13:45 +10:00
32f6a58db2
add initial drm_fb framebuffer
...
So far I can load fbcon, once I use my miniglx to add a framebuffer.
fbcon doesn't show anything on screen but baby steps and all that.
2007-04-11 16:33:03 +10:00
add7a928ad
comment out unworkable code
2007-04-11 14:43:02 +10:00
3dd5dc5728
only init at driver load
2007-04-11 14:34:43 +10:00
b329f91502
use the baseaddr at least
2007-04-11 14:04:18 +10:00
44be9c9d59
add an fb count + id get to the get resources code path
2007-04-11 13:26:21 +10:00
9b7211dd67
nouveau: nv10 per channel init from ddx
2007-04-10 23:20:13 +02:00
44a8761302
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
...
Conflicts:
linux-core/drm_crtc.c - trivial merge
linux-core/drm_crtc.h - trivial merge
linux-core/intel_display.c - crtc_config -> mode_config
shared-core/i915_dma.c - accommodate new init code in i915_init.c
2007-04-10 10:45:55 -07:00
b59285d738
Move i915 init code to new file, i915_init.c, and create a new high level
...
init routine that runs at driver load time.
2007-04-10 10:31:10 -07:00
5130918e25
Add save/restore state for LVDS code, along with a few other LVDS related
...
items to i915 private structure.
2007-04-10 09:51:17 -07:00
1e39dc4323
export output name to userspace
2007-04-10 16:25:31 +10:00
40bd6dcd86
set the base address of the CRTC correctly
2007-04-10 15:20:50 +10:00
65f465ed5a
fixup numerous issues with adding framebuffer support
...
This still isn't perfect but it fixes a few oopses and cleans up
some of the tabs and bugs in the original fb limit code
2007-04-10 14:49:49 +10:00
b50bda002b
add addfb/rmfb ioctls
...
Originally from Jakob, cleaned up by airlied.
2007-04-10 18:44:47 +10:00
059b5d9077
rs480: Renamed some unknown registers. See dri-devel list.
2007-04-09 23:23:40 +00:00
2d7f9f59c3
nouveau: NV46 support
2007-04-09 23:20:26 +10:00
29f8fe8046
radeon: bump version for IGPGART support
2007-04-09 22:00:34 +10:00
a70f8e0ab2
radeon: add support for reverse engineered xpress200m
...
The IGPGART setup code was traced using mmio-trace on fglrx by myself
and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel.
This code doesn't let the 3D driver work properly as the card has no
vertex shader support.
Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this
work on.
2007-04-09 21:52:59 +10:00
46257c51c1
i915: use breadcrumb macro everywhere
2007-04-06 20:21:44 +10:00
78034c06df
nouveau: make a note about a bit that breaks some cards
2007-04-06 03:27:55 +10:00
38f52402a8
nouveau: Power up all card units by default on startup.
2007-04-06 03:26:19 +10:00
b4094864f1
checkpoint commit: implement SetCrtc so modes can in theory be set from user
...
This hooks up the userspace mode set it "seems" to work.
2007-04-05 18:01:02 +10:00
7bb112feca
checkpoint commit: added getresources, crtc and output
...
This adds the user interfaces from Jakob and hooks them up for 3 ioctls
GetResources, GetCrtc and GetOutput.
I've made the ids for everything fbs, crtcs, outputs and modes go via idr as
per krh's suggestion on irc as it make the code nice and consistent.
2007-04-05 17:06:42 +10:00
5bffbd6e27
initial userspace interface to get modes
2007-04-05 13:34:50 +10:00
52f9028c84
Initial import of modesetting for intel driver in DRM
2007-04-05 11:21:06 +10:00
139e4bbc73
Make sure we ack irqs before we read a breadcrumb so that
...
breadcrumb updates that occur _AFTER_ we've read the breadcrumb really
generates a new IRQ.
2007-04-03 10:29:15 +02:00
5395a92d40
r300: Synchronize the register header file again.
...
It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
2007-04-02 19:45:10 +00:00
cbbdbd5e65
nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+
...
http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file.
Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e , NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
2007-04-01 14:31:41 +02:00
25cedcf76f
nouveau : nv10 ctx switch fix
...
restoring NV10_PGRAPH_CTX_SWITCH1 now works
2007-04-01 14:21:29 +02:00
bdc5a8b62e
radeon: enable buffer manager
2007-04-01 19:09:00 +10:00
b1f0b2d960
radeon: de-static irq function, fixup fence/buffer
2007-04-01 18:24:23 +10:00
be5bf1346e
copy over some files and reorg radeon to add ttm fencing not working yet
2007-04-01 16:48:38 +10:00
223061e084
nouveau : set the correct PGRAPH_CTX_CONTROL register
...
"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-04-01 00:44:11 +02:00
ddb1715e06
Merge branch 'crestline-qa', adding support for the 965GM chipset.
2007-03-30 13:11:39 -07:00
bdabc8f998
nouveau: fix nv04 context switches.
2007-03-29 00:54:18 +02:00
81b811da37
drm/i915: set the bo up at firstopen time not after DMA init
...
This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
406a894e52
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-27 12:53:13 +08:00
674cefd4fe
nouveau: move card initialisation into the drm
...
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
e7cd5a1e2d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-23 17:00:41 +08:00
4988fa4886
nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
2007-03-23 15:25:37 +11:00
2bb9de96d5
nouveau: remove unused cruft
2007-03-23 13:45:29 +11:00
0467ad4118
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-21 17:00:43 +08:00
e22225416a
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 17:57:47 +11:00
8398b99d8d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-19 17:00:31 +08:00
26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
...
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
...
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
...
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
...
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
...
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
6c48b8e7ff
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-01 09:02:09 -05:00
72caa48c82
nouveau: intrusive drm interface changes
...
graphics objects:
- No longer takes flags/dmaobj parameters, requires some major changes
to the ddx to setup the object through the FIFO. This change is
likely to cause breakages on some cards (tested on NV05,NV28,NV35,
NV40 and NV4E).
dma objects:
- now takes a "class" parameter, not really used yet but we may need
it at some point.
- parameters are checked, so clients can't randomly create DMA objects
pointing at whatever they feel like.
misc:
- Added FB_SIZE/AGP_SIZE getparams
- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
df2fc3ec62
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-02-25 17:06:13 -08:00
9d8ba2d0d4
drm: remove unnecessary NULL checks, and fix some indents..
2007-02-25 10:48:26 +11:00
e0f53e59be
Simple fence object sample driver for via, based on idling the GPU.
...
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
7766378d97
Initial support for fence object classes.
...
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
a78f70faad
Merge branch 'ttm-vram-0-1-branch'
2007-02-14 15:33:40 +01:00
5c9a7b0f94
Remove an intel-specific hack and replace it with a fence driver callback.
2007-02-14 13:31:35 +01:00
f524870184
nouveau: fix the build on big endian (thanks CyberFoxx)
2007-02-14 00:08:55 +01:00
59af900e4f
nouveau: fix memory initialization with multiple cards.
2007-02-14 00:07:31 +01:00
e1460426b8
Bugzilla Bug #9457
...
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.
Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.
It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
80095ffe01
i915: Add 965GM pci id update
2007-02-13 16:20:45 +08:00
abc14ddfb5
Update flags and comments.
2007-02-12 21:40:42 +01:00
130c39be3c
Sync r300_reg.h from mesa driver. #10210
2007-02-11 10:24:14 +02:00
4f795a05f1
Merge branch 'i915-pageflip'
2007-03-10 00:11:10 +01:00
d734992e6a
i915: Only wait for pending flips before asynchronous flips again.
2007-03-10 00:10:49 +01:00
0741064df4
i915: Do not wait for pending flips on both pipes at the same time.
...
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
1b3a6d4775
nouveau: remove a hack that's not needed since the last interface change.
2007-03-07 21:17:45 +11:00
5bd0e52dba
nouveau: ack PFIFO interrupts at PFIFO, not PMC.
2007-03-07 21:00:55 +11:00
a33859184a
i915: Eliminate dev_priv->current_page.
...
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
074e10b384
i915: Only clean up page flipping when the last client goes away, not any one.
2007-02-28 15:57:08 +01:00
1cdc1b6fba
i915: Don't emit waits for pending flips before emitting synchronous flips.
...
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.
Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
fd0fed3f1e
i915: Fix test for synchronous flip affecting both pipes.
2007-02-28 12:33:56 +01:00
1a0d890a42
i915: Add support for scheduled buffer swaps to be done as flips.
...
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
5a40c043cc
Add DRM_VBLANK_FLIP.
...
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
6f89584e13
i915: Improved page flipping support, including triple buffering.
...
Pages are tracked independently on each pipe.
Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
34aa3393d0
i915: Page flipping enhancements.
...
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.
Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
078e430726
i915: Unify breadcrumb emission.
2007-02-19 15:08:40 +01:00
53aee3122a
I915 accelerated blit copy functional.
...
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
898aca1a66
Warning fix: correct type of i915_mmio argument.
2007-02-07 21:26:02 -08:00
ef9a9d3cd1
Define __iomem for systems without it.
2007-02-07 21:26:01 -08:00
8918748058
Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.
2007-02-07 21:26:01 -08:00
c1fbd8a566
Checkpoint commit.
...
Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
609e3b0375
Implement a policy for selecting memory types.
2007-02-06 14:20:33 +01:00
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
0c13657c33
nouveau: plugin the nv04 graph init function.
2007-02-03 06:00:29 +01:00
7ab9e7f36f
nouveau: cleanup the nv04 pgraph save/restore mechanism.
2007-02-03 05:56:42 +01:00
d69902db3b
nouveau: fix nv04 graph routines for new register names.
2007-02-03 05:25:36 +01:00
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
6c04185857
via: Try to improve command-buffer chaining.
...
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
3024f23c65
memory manager: Make device driver aware of different memory types.
...
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
06cd155595
nouveau: opps restored the wrong channel
2007-01-13 23:30:43 +01:00
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
4ae64a1b58
nouveau: add and indent pgraph regs
2007-01-13 21:44:50 +01:00
1967aa82cf
nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.
2007-01-13 12:32:50 +01:00
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
9d3deddc4a
Delay for a usec while spinning waiting for ring buffer space.
...
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times. This matches other drivers' behavior when waiting for ring buffer/fifo
space.
2007-01-12 11:24:50 -08:00
4297a83b48
nouveau: get nv30 context switching to work.
...
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
8ff026723c
radeon: Fix u32 overflows when determining AGP base address in card space.
...
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.
See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-11 09:02:07 +01:00
a70aedd5fc
novueau: try resource 3 if resource 2 is 0 length
...
This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
deba42ef32
nouveau: fix nv4a context size.
2007-01-08 20:55:57 +01:00
d0080d71b9
nouveau: nv4a context support.
2007-01-08 05:02:40 +01:00
6eaa1272b4
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-08 03:50:34 +01:00
26bf6d9b5b
nouveau: oops
2007-01-08 12:50:44 +11:00
128d87a3dd
nouveau: nv43 context stuff
2007-01-08 12:47:51 +11:00
1f0f7d7a18
nouveau: fix a stupid bug from me.
2007-01-08 00:11:39 +01:00
faa4612299
nouveau: avoid allocating vram that's used as instance memory.
2007-01-08 00:44:02 +11:00
cd3711455e
nouveau: map pci resource 2 on >=nv40
2007-01-08 00:44:02 +11:00
31daf66962
Revert i915 drm driver name to i915; miniglx doesn't work otherwise
...
Yes, this driver supports the new memory manager, that is indicated by the
version number being >= 1.7.
2007-01-06 17:40:50 -08:00
2851c9f5c6
Bump i915 minor for ARB_OC ioctl
2007-01-06 16:26:54 -08:00
f7180349fd
i915: ARB_Occlusion_query(MMIO ioctl) support.
...
This adds a new ioctl for passing counter information from the chip back to
applications, these counters include the data needed to perform OC.
2007-01-06 16:22:08 -08:00
1f1714cf3d
nouveau: get c51 doing glxgears without the binary driver's help.
2007-01-06 18:05:21 +11:00
dbb0d979cc
nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.
2007-01-06 17:50:00 +11:00
528ab8ce40
nouveau: oops, we don't need OS_HAS_MTRR actually.
2007-01-05 20:59:45 +01:00
d99c7c27e2
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-05 20:50:46 +01:00
025f281bbf
nouveau: Add an mtrr over the whole FB
2007-01-05 20:49:34 +01:00
0f95ddc428
Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/
2007-01-05 19:41:12 +01:00
9d167f1f4b
Add basic pgraph context for nv10.
...
It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
f80659bc29
Cleanup the nv04 fifo code a bit.
2007-01-05 19:37:06 +01:00
4fe2858f53
i915: Fix a DRM_ERROR that should be DRM_DEBUG.
...
It would clutter up the kernel output in a situation which is legitimate before
X.org 7.2 and handled correctly by the 3D driver.
2007-01-02 10:05:48 +01:00
91855bb254
nouveau: oops, forgot to free RAMIN..
2007-01-02 16:35:00 +11:00
861017e6d5
nouveau: Hookup nv40_graph_init.
...
Now I can get 3D + working grctx switching on my NV40 without
the binary driver initialising the card first. However, this
change also breaks 3D on my C51 even *with* the binary driver's
help. So, it's likely that the weird voodoo is card-specific.
2007-01-02 15:56:10 +11:00
41da9fd2e5
nouveau: Hook up grctx code for NV4x.
...
This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.
Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
0e0d954584
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-02 14:52:43 +11:00
2c3bc69ba2
nouveau: Only clobber PFIFO if no channels are already alloc'd
...
With this change the GPU is responsible for doing the channel switch
itself. This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
a16a8a47cd
Add some new via chipsets.
...
Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.
2006-12-28 22:17:08 +01:00
7859bd61d3
Leftover from previous commit.
2006-12-27 19:46:46 +01:00
2980ec22a1
Allow for non-power-of-two texture pitch alignment.
2006-12-27 19:38:33 +01:00
c38ede0667
nouveau: return the *actual* type of memory alloc'd to userspace
2006-12-27 01:58:57 +11:00
9e019df757
nouveau: Alloc cmdbuf for each channel individually
2006-12-26 23:30:26 +11:00
b7586ab539
nouveau: save/restore endianness flag on FIFO switch
...
This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
3b47b27558
Some via PCI posting flushes.
2006-12-20 13:04:21 +01:00
e5c4a26a29
Merge branch 'nouveau-1'
2006-12-20 10:30:16 +11:00
7458909bea
fixup i915 return values from kernel
2006-12-19 21:48:18 +11:00
07635f26a9
fix comment in r128
2006-12-19 17:58:20 +11:00
c52dea9a7d
fix some sizes in sis_drv.h
2006-12-19 17:58:16 +11:00
8cc82c5033
remove inline from large function
2006-12-19 17:58:12 +11:00
13659357ad
make a savage function static from kernel
2006-12-19 17:58:09 +11:00
cb280ad3c0
fix missing DRM_ERR from kernel
2006-12-19 17:58:03 +11:00
aefc7a3443
Unify radeon offset checking.
...
Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697 .
2006-12-14 19:31:56 +01:00
1a40f3318c
Port remaining NV4 RAMIN access from the ddx into the drm.
...
Should fix lockups seen on NV4 cards.
2006-12-12 00:11:42 +11:00
30acb90a60
Merge the pciid work.
...
Add getparams for AGP and FB physical adresses.
Fix the MEM_ALLOC issue properly.
Fix context switches for nv44.
Change the DRM version to 0.0.1.
2006-12-03 10:02:54 +01:00
a97bb85c2a
Unshare drm_drawable.c again for now.
...
The current version didn't build on BSD, where the new functionality isn't used
yet anyway. Whoever changes that will hopefully be able to make the OSes share
this file as well.
2006-12-01 10:46:21 +01:00
80d75cf695
Use nouveau_mem.c to allocate RAMIN.
2006-11-30 10:31:42 +11:00
b1a9a76971
Wrap access to objects in RAMIN.
...
This will make it easier to support extra RAMIN in vram at a later point.
2006-11-30 08:35:42 +11:00
f48a7685bd
For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
...
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
ddcb994c3e
i915_vblank_tasklet: Try harder to avoid tearing.
...
Previously, if there were several buffer swaps scheduled for the same vertical
blank, all but the first blit emitted stood a chance of exhibiting tearing. In
order to avoid this, split the blits along slices of each output top to bottom.
2006-11-27 11:32:33 +01:00
0a364be289
Merge branch 'nouveau-1' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-21 23:32:58 +01:00
adf71cb29b
Don't spam dmesg if PMC_INTSTAT is 0
2006-11-21 11:41:46 +11:00
9ac7a8b0b4
Only return FIFO number if the FIFO is marked as in use..
2006-11-18 10:09:29 +11:00
e9194dd1b0
Check some return vals, fixes a couple of oopses.
2006-11-18 10:03:45 +11:00
18bba3fa29
Dump some useful info when a PGRAPH error occurs.
...
The "channel" detect doesn't work on my nv40, but the rest
seems to produce sane info.
2006-11-17 08:05:23 +11:00
5e7f58474d
Merge branch 'nouveau-1' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-16 14:47:52 +01:00
2fd812f8ef
Completely untested NV10/20/30 FIFO context switching changes.
2006-11-14 09:00:31 +11:00
7002082944
Restructure initialisation a bit.
...
- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
35bf8fb5cf
Merge branch 'nouveau-1' of git+ssh://git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-14 04:52:08 +11:00
9ef4bbc66c
Hack around yet another "X restart borkage without nouveau.ko reload" problem.
...
On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to
loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
2006-11-14 04:51:13 +11:00
5a0cdf7db3
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-11 01:57:05 +01:00
1123ab0890
Fix memory detection on TNT2 M64/TNT2 vanta.
2006-11-10 02:18:38 +01:00
584acab6d6
Add drm_u64_t typedef on non-linux to fix libdrm build.
2006-11-07 09:36:40 -08:00
f7affda35b
drm: fixup page alignment on SAREA map on ppc64
2006-11-06 11:44:36 +11:00
2dd3c039fd
fixup fifo size so it is page aligned
2006-11-06 11:42:15 +11:00
5e55594061
use a uint64_t for this not a pointer
2006-11-06 11:41:51 +11:00
1e90b7ee8c
Merge branch 'master' into nouveau-1
...
Conflicts:
linux-core/Makefile.kernel
2006-11-06 08:03:18 +11:00
0c34d0f31a
Leave the bottom 64kb of RAMIN untouched.
...
The binary driver will screw up either it's init or shutdown, leaving the
screen(s) in an unusable state without this. Something important in there?
2006-11-06 05:46:03 +11:00
94ab96c4d8
nouveau: add compat ioc32 support
2006-11-05 20:39:13 +11:00
665c8385c7
add powerpc mmio swapper to NV_READ/WRITE macros
2006-11-05 19:46:53 +11:00
06639801ce
Add some getparams.
2006-11-04 20:39:59 +01:00
3ea0500be1
Move the context object creation flag handling to the drm.
2006-11-04 16:56:10 +01:00
decacb2e64
Reserve the new IOCTLs also for *bsd.
...
Bump libdrm version number to 2.2.0
2006-10-27 13:08:31 +02:00
f6d5fecdd2
Last minute changes to support multi-page size buffer offset alignments.
...
This will come in very handy for tiled buffers on intel hardware.
Also add some padding to interface structures to allow future binary backwards
compatible changes.
2006-10-27 11:28:37 +02:00
d70347bfc0
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm
2006-10-19 17:07:26 +02:00
e22b04f807
Merging drm-ttm-0-2-branch
...
Conflicts:
linux-core/drmP.h
linux-core/drm_drv.c
linux-core/drm_irq.c
linux-core/drm_stub.c
shared-core/drm.h
shared-core/i915_drv.h
shared-core/i915_irq.c
2006-10-18 17:33:19 +02:00
c34faf224b
Remove max number of locked pages check and call, since
...
that is now handled by the memory accounting.
2006-10-17 20:03:26 +02:00
b5cf0d635c
Remove hack which delays activation of a additional channel. The previously active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-18 02:37:19 +11:00
725984364b
Oops, we have more than 4 subchannels..
2006-10-18 01:07:48 +11:00
55de3f763f
Useful output on a FIFO error interrupt.
2006-10-17 23:44:05 +11:00
07059f4278
typo
2006-10-17 23:08:03 +11:00
5881ce1b91
Extend generality for more memory types.
...
Fix up init and destruction code.
2006-10-17 11:05:37 +02:00
561e23a7c2
dev->agp_buffer_map is not initialized for AGP DMA on savages
...
bug 8662
2006-10-16 22:06:58 -04:00
4b43ee63f9
NV40: *Now* fifo ctx switching works for me..
...
Ok, I lied before.. it was a fluke it worked and required magic to repeat it..
It actually helps to fill in RAMFC entries in the correct place.
The code also clears RAMIN entirely instead of just the hash-table.
2006-10-17 12:33:49 +11:00
98e718d48f
NV40: FIFO context switching now WorksForMe(tm)
2006-10-17 07:29:31 +11:00
1943f39d8c
Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup code a bit.
2006-10-17 06:37:40 +11:00
95486bbde0
Some info on NV40's RAMFC
2006-10-17 06:12:18 +11:00
93fee5cf22
Merge branch 'master' of git://anongit.freedesktop.org/git/mesa/drm into nouveau-1
2006-10-15 00:12:13 +02:00
2c5b91aecf
Again more work on context switches. They work, sometimes. And when they do they seem to screw up the PGRAPH state.
2006-10-14 16:36:11 +02:00
1bab514c0a
remove config.h from build no longer exists kbuild does it
2006-10-14 23:38:20 +10:00
3a0cd7c7e2
Add the missing breaks.
2006-10-14 01:21:31 +02:00
b509abe413
Fix the fifo context size on nv10, nv20 and nv30.
2006-10-13 22:35:22 +02:00
4988074794
Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals). Ch 1 GET now advances, but no ctx_switch.
2006-10-14 06:57:49 +11:00
a9c6c3f21d
Oops.
2006-10-12 21:18:55 +02:00
7ef44b2b8d
Still more work on the context switching code.
2006-10-12 17:31:49 +02:00
10150df02b
Simplify the AGP backend interface somewhat.
...
Fix buffer bound caching policy changing, Allow
on-the-fly changing of caching policy on bound buffers if the hardware
supports it.
Allow drivers to use driver-specific AGP memory types for TTM AGP pages.
Will make AGP drivers much easier to migrate.
2006-10-12 12:09:16 +02:00
a749d9d5b4
More work on the context switch code. Still doesn't work. I'm mostly convinced it's an initialization issue.
2006-10-12 01:08:15 +02:00
f2db76e2f2
Big update:
...
Adapt for new functions in the 2.6.19 kernel.
Remove the ability to have multiple regions in one TTM.
This simplifies a lot of code.
Remove the ability to access TTMs from user space.
We don't need it anymore without ttm regions.
Don't change caching policy for evicted buffers. Instead change it only
when the buffer is accessed by the CPU (on the first page fault).
This tremendously speeds up eviction rates.
Current code is safe for kernels <= 2.6.14.
Should also be OK with 2.6.19 and above.
2006-10-11 13:40:35 +02:00
dd473411f8
Context switching work.
...
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
2006-10-11 00:28:15 +02:00
a9f57a2b9c
only allow specific type-3 packets to pass the verifier instead of all for r100/r200 as others might be unsafe (r300 already does this), and add checking for these we need but aren't safe. Check the RADEON_CP_INDX_BUFFER packet on both r200 and r300 as it isn't safe neither.
2006-10-10 02:24:19 +02:00
c9e3aa961e
Bug 6242: [mach64] Use private DMA buffers, part #4 .
...
mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to
user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX.
This change allows the DDX to map the DMA buffers read-only and eliminate a
security problem where a client can alter the contents of the DMA buffer after
submission to the DRM.
This change also affects the DRI/DRM interface. Performace-wise, it basically
affects PCI mode where I get a ~12% speedup for some Mesa demos I tested.
This is mainly due to eliminating an ioctl for allocating the DMA buffer.
mach64_dma.c: move the responsibility for allocating memory for the DMA ring
in PCI mode to the DDX.
This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code
paths for ring memory in the DRM.
Bump the mach64 DRM version major and date.
2006-10-02 22:47:26 +03:00
f3deef730d
Bug 6242: [mach64] Use private DMA buffers, part #3 .
...
Add DRM_PCI_BUFFER_RO flag for mapping PCI DMA buffer read-only. An additional
flag is needed, since PCI DMA buffers do not have an associated map.
2006-10-02 22:47:23 +03:00
25760c30d4
Bug 6242: [mach64] Use private DMA buffers, part #2 .
...
Factor out from mach64_dma_dispatch_vertex() the code to reclaim an unsed
buffer, in preperation for using it in mach64_dma_dispatch_blit() also.
2006-10-02 22:47:19 +03:00
eea150e776
Bug 6242: [mach64] Use private DMA buffers, part #1 .
...
Factor out from mach64_freelist_get() the code to reclaim a completed buffer,
this is to improve readability for me.
2006-10-02 22:47:14 +03:00
d1b31a228b
Bug 6209: [mach64] AGP DMA buffers not mapped correctly.
...
Map the DMA buffers from the same linear address as the vertex bufs. If
dev->agp_buffer_token is not set, mach64 drm maps the DMA buffers from
linear address 0x0.
2006-10-02 22:46:54 +03:00
16be6ba63a
Fix type of second argument to spin_lock_irqsave().
...
(cherry picked from f6238cf624
2006-10-02 15:42:07 +02:00
f6238cf624
Fix type of second argument to spin_lock_irqsave().
2006-10-02 15:33:19 +02:00
58a23d193f
drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.
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(cherry picked from d583899681
2006-10-02 11:21:10 +02:00
d583899681
drm_rmdraw: Declare id and idx as signed so testing for < 0 works as intended.
2006-10-02 10:50:40 +02:00
8e908eaf50
Bump driver date.
2006-09-29 14:21:51 +02:00
17a640419a
i915: Only schedule vblank tasklet if there are scheduled swaps pending.
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This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
(cherry picked from 7af93dd984
2006-09-29 12:55:09 +02:00
48367fdfe6
i915: Only initialize IRQ fields in postinstall, not the PIPE_SET ioctl.
...
Some other minor changes in preparation for actually disabling user interrupts.
2006-09-29 12:55:09 +02:00
3620a3ec85
i915: Bump minor again to differentiate from vsync changes.
2006-09-29 12:55:09 +02:00
390184df92
i915: Avoid mis-counting vblank interrupts when they're only enabled for pipe A.
...
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
(cherry picked from 881ba56992
2006-09-29 12:55:09 +02:00
c0bff9f9cd
i915: Bump minor for swap scheduling ioctl and secondary vblank support.
...
(cherry picked from 2627131e5d
2006-09-29 12:55:09 +02:00
0a7d9edcfb
i915_vblank_swap: Add support for DRM_VBLANK_NEXTONMISS.
...
(cherry picked from 0356fe260d
2006-09-29 12:55:09 +02:00
c47ebd9707
Only return EBUSY after we've established we need to schedule a new swap.
...
(cherry picked from 50a0284a61
2006-09-29 12:55:09 +02:00
ed82172378
Core vsync: Add flag DRM_VBLANK_NEXTONMISS.
...
When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
(cherry picked from 89e323e490
2006-09-29 12:55:08 +02:00
c4c47a7eac
Fix 'sequence has passed' condition in i915_vblank_swap().
...
(cherry picked from 7f09f957d9
2006-09-29 12:55:08 +02:00
f9aa4f5973
Add SAREA fileds for determining which pipe to sync window buffer swaps to.
...
(cherry picked from c2bdb76814
2006-09-29 12:55:08 +02:00
4a3d270862
Make handling of dev_priv->vblank_pipe more robust.
...
Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
(cherry picked from 87c57cba1a
2006-09-29 12:55:08 +02:00
1f3493f65b
DRM_I915_VBLANK_SWAP ioctl: Take drm_vblank_seq_type_t instead of pipe number.
...
Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
(cherry picked from d5a0f10751
2006-09-29 12:55:08 +02:00
00531cecad
Change first valid DRM drawable ID to be 1 instead of 0.
...
This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
(cherry picked from df7551ef73
2006-09-29 12:55:08 +02:00
7d487602a3
Add copyright notice.
...
(cherry picked from d04751face
2006-09-29 12:55:08 +02:00
da75d59cd6
i915: Add ioctl for scheduling buffer swaps at vertical blanks.
...
This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
(cherry picked from 257771fa29
2006-09-29 12:55:08 +02:00
d7389a9758
Locking and memory management fixes.
...
(cherry picked from 23d2833aaa
2006-09-29 12:55:08 +02:00
f93e482269
Export drm_get_drawable_info symbol from core.
...
(cherry picked from 43f8675534
2006-09-29 12:55:08 +02:00
baa26c5faa
Only reallocate cliprect memory if the number of cliprects changes.
...
Also improve diagnostic output.
(cherry picked from af48be1096
2006-09-29 12:55:08 +02:00
9810ec2737
Add support for tracking drawable information to core
...
Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
(cherry picked from 29598e5253
2006-09-29 12:55:08 +02:00
596d7e9984
Add support for secondary vertical blank interrupt to i915 driver.
...
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
(cherry picked from 0c7d7f4361
2006-09-29 12:55:08 +02:00
2735f9e290
Add support for secondary vertical blank interrupt to DRM core.
...
(cherry picked from ab351505f3
2006-09-29 12:55:08 +02:00
ae96e26419
Add a new buffer flag.
...
Fix up some comments.
2006-09-29 11:46:45 +02:00
7af93dd984
i915: Only schedule vblank tasklet if there are scheduled swaps pending.
...
This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
2006-09-29 10:27:29 +02:00
881ba56992
i915: Avoid mis-counting vblank interrupts when they're only enabled for pipe A.
...
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
2006-09-28 15:41:36 +02:00
2627131e5d
i915: Bump minor for swap scheduling ioctl and secondary vblank support.
2006-09-28 15:41:36 +02:00
0356fe260d
i915_vblank_swap: Add support for DRM_VBLANK_NEXTONMISS.
2006-09-28 15:41:36 +02:00
50a0284a61
Only return EBUSY after we've established we need to schedule a new swap.
2006-09-28 15:41:36 +02:00
89e323e490
Core vsync: Add flag DRM_VBLANK_NEXTONMISS.
...
When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
2006-09-28 15:41:36 +02:00
7f09f957d9
Fix 'sequence has passed' condition in i915_vblank_swap().
2006-09-28 15:41:36 +02:00
c2bdb76814
Add SAREA fileds for determining which pipe to sync window buffer swaps to.
2006-09-28 15:41:36 +02:00
87c57cba1a
Make handling of dev_priv->vblank_pipe more robust.
...
Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
2006-09-28 15:41:36 +02:00
d5a0f10751
DRM_I915_VBLANK_SWAP ioctl: Take drm_vblank_seq_type_t instead of pipe number.
...
Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
2006-09-28 15:41:36 +02:00
df7551ef73
Change first valid DRM drawable ID to be 1 instead of 0.
...
This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
2006-09-28 15:41:36 +02:00
d04751face
Add copyright notice.
2006-09-28 15:41:36 +02:00
257771fa29
i915: Add ioctl for scheduling buffer swaps at vertical blanks.
...
This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
2006-09-28 15:41:36 +02:00
23d2833aaa
Locking and memory management fixes.
2006-09-28 15:41:36 +02:00
43f8675534
Export drm_get_drawable_info symbol from core.
2006-09-28 15:41:35 +02:00
af48be1096
Only reallocate cliprect memory if the number of cliprects changes.
...
Also improve diagnostic output.
2006-09-28 15:41:35 +02:00
29598e5253
Add support for tracking drawable information to core
...
Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
2006-09-28 15:41:35 +02:00
0c7d7f4361
Add support for secondary vertical blank interrupt to i915 driver.
...
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
2006-09-28 15:41:35 +02:00
ab351505f3
Add support for secondary vertical blank interrupt to DRM core.
2006-09-28 15:41:35 +02:00
c52fafa628
Don't enable fence / buffer objects on non-linux systems.
...
Bump driver minor and date.
2006-09-28 11:33:03 +02:00
273eb7833d
Add /proc filesystem buffer / fence object accounting.
...
Check for NULL pointer in the i915 flush handler.
Remove i915_sync_flush declaration.
2006-09-25 11:51:08 +02:00
255f3e6f76
bug 7092 : add pci ids for mach64 in Dell poweredge 4200
2006-09-22 03:43:34 +10:00
1f71b8d7a4
do a TCL state flush before accessing VAP_CNTL to prevent lockups on r200 when enabling/disabling vertex programs
2006-09-20 19:44:57 +02:00
fa511a3ff5
Allow for 64-bit map handles of ttms and buffer objects.
2006-09-20 16:31:15 +02:00
22382bd8c5
Add pciid for GeForce Go 6150 (0x0244).
2006-09-17 13:00:27 +10:00
6ba9127753
Use register writes instead of BITBLT_MULTI packets for buffer swap blits.
...
This takes up two more ring buffer entries per rectangle blitted but makes sure
the blit is performed top to bottom, reducing the likelyhood of tearing.
2006-09-15 16:55:40 +02:00
f613022cee
Allow a "native type" to be associated with a fence sequence.
...
In the intel case, we can associate a flush with a sequence.
2006-09-15 16:47:09 +02:00
49fbeb339c
Some bugfixes.
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Change the fence object interface somewhat to allow some more flexibility.
Make list IOCTLS really restartable.
Try to avoid busy-waits in the kernel using immediate return to user-space with an -EAGAIN.
2006-09-15 11:18:35 +02:00
191e284709
More bugfixes.
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Disable the i915 IRQ turnoff for now since it seems to be causing problems.
2006-09-12 12:01:00 +02:00
3cc64a943a
drm: use radeon specific names for radeon flags
2006-09-12 06:13:14 +10:00
aa80e2f48f
Add copyright notices while I still remember..
2006-09-09 07:35:55 +10:00
99acb79366
Various bugfixes.
2006-09-08 17:24:38 +02:00
0ef29768ca
Fix second start of X server without module reload beforehand, and a couple of other fixes.
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- Mark the correct RAMIN slots as free (oops)
- Remove a VRAM alloc that shouldn't have been there (oops)
- Move HT init out of firstopen() and into dma_init()
- Setup PFIFO_RAM{HT,FC,RO} in pfifo_init()
2006-09-07 23:59:19 +10:00
55057660f0
Put the PCI device/vendor id in the drm_device_t.
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This helps us unbreak FreeBSD DRM from the 965 changes.
2006-09-06 23:25:14 -07:00
d89c623f8e
Remove a 64 bit div.
2006-09-07 00:35:17 +02:00
6042153968
Fence all unfenced buffers function.
2006-09-05 18:00:25 +02:00
034fc31292
i915: Only turn on user IRQs when they are needed.
2006-09-05 14:23:18 +02:00
550f51b4bf
Buffer object wait IOCTL operation.
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Remove option to wait for fence / buffers and block signals.
2006-09-04 21:50:12 +02:00
b119966ae6
Allow cmdbuf location(AGP,VRAM) and size to be configured.
2006-09-03 06:36:06 +10:00
97291a6ad0
Use DMA_IN_MEMORY for DMA objects. This is needed for a DDX change that will
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be committed soon after this. Without the change, MEMFORMAT_DMA_OUT appears
to have no effect.
2006-09-02 22:25:26 +10:00
405b5d9ca8
Flag bit pattern bugfixes. Remove some error messages.
2006-09-01 18:11:05 +02:00
ef8e618cf3
Export buffer info on map and validate ioctls.
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Add an info ioctl operation.
2006-09-01 16:38:06 +02:00
44f6d08988
Validation and fencing.
2006-08-31 21:42:29 +02:00
ec8c79b79d
More mapping synchronization.
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libdrm validate and fencing functions.
2006-08-31 14:10:13 +02:00
d39055174b
Remove the buffer object hint field and use it only
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as an argument.
Validate stub.
2006-08-30 17:40:07 +02:00
e47a4fda2e
Memory manager init and takedown.
2006-08-30 13:04:08 +02:00
033bda07e9
Buffer object reply fill in.
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Lindent of drm_bo.c drm_ttm.c
2006-08-30 09:57:35 +02:00
24dddc2754
Add stub {get,set}param ioctls.
2006-08-30 16:55:02 +10:00
de144ba23c
Part of buffer object libdrm interface.
2006-08-29 21:57:37 +02:00
23f01c9fe8
Checkpoint commit. Buffer object flags and IOCTL argument list.
2006-08-29 18:40:08 +02:00
0dedfc2cd0
Checkpoint ttm addition to buffer objects.
2006-08-29 14:52:02 +02:00
279e8d26c6
64-bit IOCTL integer (Michel Dnzer & Brian Paul)
2006-08-29 10:45:34 +02:00
2057406470
Buffer object creation.
2006-08-28 17:51:53 +02:00
0d67356de4
Proper TTM dereferencing
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Initial buffer object creation.
2006-08-28 16:36:37 +02:00
3cfab681b3
Merge branch 'master' into nouveau-1
2006-08-29 00:01:19 +10:00
e181f594a4
Add a 64-bit drm unsigned type for 64-bit clean IOCTLS.
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Conversion functions in drmP.h and xf86drm.c.
2006-08-28 09:49:09 +02:00
4ddabd1562
Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into drm-ttm-0-2-branch
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Conflicts:
linux-core/drmP.h
2006-08-28 09:28:10 +02:00
9b984b34e9
drm: lots of small cleanups and whitespace issues fixed up
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remove a mach64 warning, align a lot of things from linux kernel
2006-08-28 11:31:43 +10:00
928bdc6c1c
Initialize i915 saved flush flags.
2006-08-27 21:21:06 +02:00
b4b7b99760
Remove the ioctl multiplexing, and instead allow for generic
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drm ioctls 0x80 - 0xFF.
2006-08-27 21:16:13 +02:00
65e7274008
ttm create / destroy / ref / unref ioctl.
2006-08-27 19:03:20 +02:00
88928380c8
add pci ids for nouveau
2006-08-27 08:59:50 +10:00
Ben Skeggs
Thomas Hellstrom
Ian Romanick
Jesse Barnes
Michel Dänzer
Jesse Barnes
Oliver McFadden
Jesse Barnes
Alex Deucher
Wang Zhenyu
Dave Airlie
Maurice van der Pot
Dave Airlie
Jung-uk Kim
Thomas Gleixner
Alan Hourihane
Matthieu Castet
Keith Packard
George Sapountzis
Stephane Marchesin
Dave Airlie
David Airlie
Jakob Bornecrantz
Eric Anholt
Nian Wu
Patrice Mandin
Nian Wu
B. Rathmann
Aapo Tahkola
Ben Skeggs
Zou Nan hai
Jeremy Kolb
Dave Jones
Matthieu Castet
Haihao Xiang
Keith Packard
Ben Skeggs
Dave Airlie
Dave Airlie
Michael Karcher
Roland Scheidegger
Felix Kühling
Anish Mistry
Roland Scheidegger
Dave Airlie