The IGPGART setup code was traced using mmio-trace on fglrx by myself
and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel.
This code doesn't let the 3D driver work properly as the card has no
vertex shader support.
Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this
work on.
This adds the user interfaces from Jakob and hooks them up for 3 ioctls
GetResources, GetCrtc and GetOutput.
I've made the ids for everything fbs, crtcs, outputs and modes go via idr as
per krh's suggestion on irc as it make the code nice and consistent.
It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
graphics objects:
- No longer takes flags/dmaobj parameters, requires some major changes
to the ddx to setup the object through the FIFO. This change is
likely to cause breakages on some cards (tested on NV05,NV28,NV35,
NV40 and NV4E).
dma objects:
- now takes a "class" parameter, not really used yet but we may need
it at some point.
- parameters are checked, so clients can't randomly create DMA objects
pointing at whatever they feel like.
misc:
- Added FB_SIZE/AGP_SIZE getparams
- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
NOTIFICATION_PENDING.
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.
Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.
It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.
Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.
Call i915_do_cleanup_pageflip() unconditionally in preclose.
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times. This matches other drivers' behavior when waiting for ring buffer/fifo
space.
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.
See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
Now I can get 3D + working grctx switching on my NV40 without
the binary driver initialising the card first. However, this
change also breaks 3D on my C51 even *with* the binary driver's
help. So, it's likely that the weird voodoo is card-specific.
This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.
Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
With this change the GPU is responsible for doing the channel switch
itself. This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697 .
The current version didn't build on BSD, where the new functionality isn't used
yet anyway. Whoever changes that will hopefully be able to make the OSes share
this file as well.
Previously, if there were several buffer swaps scheduled for the same vertical
blank, all but the first blit emitted stood a chance of exhibiting tearing. In
order to avoid this, split the blits along slices of each output top to bottom.
- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to
loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
This will come in very handy for tiled buffers on intel hardware.
Also add some padding to interface structures to allow future binary backwards
compatible changes.
Ok, I lied before.. it was a fluke it worked and required magic to repeat it..
It actually helps to fill in RAMFC entries in the correct place.
The code also clears RAMIN entirely instead of just the hash-table.
Fix buffer bound caching policy changing, Allow
on-the-fly changing of caching policy on bound buffers if the hardware
supports it.
Allow drivers to use driver-specific AGP memory types for TTM AGP pages.
Will make AGP drivers much easier to migrate.
Adapt for new functions in the 2.6.19 kernel.
Remove the ability to have multiple regions in one TTM.
This simplifies a lot of code.
Remove the ability to access TTMs from user space.
We don't need it anymore without ttm regions.
Don't change caching policy for evicted buffers. Instead change it only
when the buffer is accessed by the CPU (on the first page fault).
This tremendously speeds up eviction rates.
Current code is safe for kernels <= 2.6.14.
Should also be OK with 2.6.19 and above.
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to
user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX.
This change allows the DDX to map the DMA buffers read-only and eliminate a
security problem where a client can alter the contents of the DMA buffer after
submission to the DRM.
This change also affects the DRI/DRM interface. Performace-wise, it basically
affects PCI mode where I get a ~12% speedup for some Mesa demos I tested.
This is mainly due to eliminating an ioctl for allocating the DMA buffer.
mach64_dma.c: move the responsibility for allocating memory for the DMA ring
in PCI mode to the DDX.
This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code
paths for ring memory in the DRM.
Bump the mach64 DRM version major and date.
Map the DMA buffers from the same linear address as the vertex bufs. If
dev->agp_buffer_token is not set, mach64 drm maps the DMA buffers from
linear address 0x0.
This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
(cherry picked from 7af93dd984 commit)
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
(cherry picked from 881ba56992 commit)
When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
(cherry picked from 89e323e490 commit)
Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
(cherry picked from 87c57cba1a commit)
Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
(cherry picked from d5a0f10751 commit)
This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
(cherry picked from df7551ef73 commit)
This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
(cherry picked from 257771fa29 commit)
Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
(cherry picked from 29598e5253 commit)
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
(cherry picked from 0c7d7f4361 commit)
It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
This takes up two more ring buffer entries per rectangle blitted but makes sure
the blit is performed top to bottom, reducing the likelyhood of tearing.
Change the fence object interface somewhat to allow some more flexibility.
Make list IOCTLS really restartable.
Try to avoid busy-waits in the kernel using immediate return to user-space with an -EAGAIN.
- Mark the correct RAMIN slots as free (oops)
- Remove a VRAM alloc that shouldn't have been there (oops)
- Move HT init out of firstopen() and into dma_init()
- Setup PFIFO_RAM{HT,FC,RO} in pfifo_init()
The overflows could cause valid offsets to get rejected under some
circumstances, e.g. when the framebuffer resides at the very end of the card's
address space.
0x00 EXE fence. Signals when command stream interpreter has reached the point
where the fence was emitted.
0x01 FLUSH fence. Signals when command stream interpreter has reached the point
where the fence was emitted, and all previous drawing operations have been
completed and flushed.
Implements busy wait (for fastest response time / high CPU) and
lazy wait (User interrupt or timer driven).
Commit 2a47f6bfec caused the CHIP_IS_AGP flag to
get 'restored' with PCI(e) cards. I can't think of a way to fix this without
introducing a (otherwise redundant) CHIP_IS_PCI flag.
Not doing this might waste bus bandwidth or even cause memory corruption or
system crashes on systems that check bus transfers. No such incident has been
reported though.
32-bit physical device addresses are mapped directly to user-tokens. No
duplicate maps are allowed, and the addresses are assumed to be outside
of the range 0x10000000 through 0x30000000. The user-token is identical
to the 32-bit physical start-address of the map.
64-bit physical device addressed are mapped to user-tokens in the range
0x10000000 to 0x30000000 with page-size increments. The user_token should
not be interpreted as an address.
Other map types, like upcoming TTM maps are mapped to user-tokens in the
range
0x10000000 to 0x30000000 with page-size increments. The user_token should
not be interpreted as an address.
This keeps compatibility with buggy drivers, while still implementing a
hashed map lookup. The SiS and via device driver major bumps are
reverted.
0x10000000 to 0x90000000 in PAGE_SIZE increments.
Implement hashed map lookups.
This potentially breaks both 2D and 3D drivers. If so, the corresponding
2D and 3D driver should be fixed, and it's corresponding drm device driver
should have its major bumped as soon as possible.
Bump sis and via drm device driver majors.
The SiS and Unichrome 3D drivers are fixed in Mesa CVS HEAD and
mesa_6_4_branch.
i915 vblanks can be generated from either pipe a or b, however a disabled
pipe generates no interrupts. This change allows the X server to select
which pipe generates vblank interrupts.
more problems with flickering (bug #6637). drm may not be appropriate
place for this, since doing that flush there might both be overkill and
insufficient in some cases. However, it's hard to figure out when that
flush is needed, so this has to suffice. There does not seem to be a
performance penalty associated with it.
Linux, which broke on FreeBSD. DRM_COPY_*_IOCTL checks for the size
parameter matching the ioctl's command size there, since the copin/out
happened earlier.
chips may be problematic). Leave the existing entries for new chips in
though. Remove ids not known by ddx (secondary ids, non-existant,...).
Correct some entries (name/family). Make the radeon family enum look
more alike the ddx/dri versions. See #5413
that particular file. Its contents have changed a good bit since the
original sis code, and the original sis code didn't care much about
attribution since it routinely disclaims Precision Insight/VA Linux
from responsibility. Also, adjust formatting around license headers
(have a comment open immediately before the "Copyright" line, not as a
runon of any previous comments) for automatic processing into FreeBSD,
where /*- is used to signal the beginning of license headers for
automatic compilation of license lists.
single DRM_COPY_FROM_USER rather than DRM_VERIFYAREA_READ followed by
tons of DRM_COPY_FROM_USER_UNCHECKED. I don't like the look of the
temporary space allocation, but I like the simplification in the rest
of the file. Tested with glxgears, tuxracer, and q3 on a savage4.
drm_mtrr_{add,del} for handling the MTRR setup. Still has a LOR issue
with DRM_VERIFYAREA_READ/DRM_COPY_FROM_USER_UNCHECKED in savage_bci.c
-- this won't work with the fine-grained locking in use, and just doing
a single copyin to a temporary will probably work fine. Also note that
the module leaks approximately 4 kb on unload.
up a good bit, I think. Also, remove the agp_uninit() function which
has lain around as a noop for years now. The FreeBSD DRM is now all
compiling, with the exception of via. One known sleeping-with-lock-held
issue remains.
radeon_cp.c to use a drm_local_map_t-type mapping (drm_core_ioremap
rather than drm_ioremap), which contains private device mapping
information on BSD. I also changed the ati_pcigart interface to use
"void *" for pointers to kva rather than "unsigned long". While PCIGART
support appears to be broken on FreeBSD currently, I think this is not
new, and BusType PCI remains working on my r100 in Linux.
drm_agp_foo_ioctl pair. Modifies the MGA DRM to use the drm_agp_foo
functions instead of the drm_foo_agp functions. The drm_foo_agp
functions are no longer exported by drm.ko.
Ensures that dma->seg_count and dma->page_count are properly set in
drm_addbufs_{agp,sg,fb}. drm_addbufs_pci was already correct.
Ensures that mga_do_agp_dma_bootstrap correctly sets agp_buffer_token.
At this point PCI DMA is still broken.
Xorg bug: #4797 Reviewed by: Dave Airlie, Eric Anholt Signed-off-by: Ian
Romanick <idr@us.ibm.com>
mga_do_agp_dma_bootstrap fails causes problems if
mga_do_pci_dma_bootstrap succeeds. This commit makes it possible to do
a "minimal" clean up instead. I'm still trying to figure out what is
causing the failures in mga_do_agp_dma_bootstrap...
Signed-off-by: Ian Romanick <idr@us.ibm.com>
R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more
regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts
instead of 6)
- Comment out the "is this mapping/bufs in allocated AGP" bits in BSD
because they break mga (which uses AGP allocation that doesn't track
entries). It's not a security issue when we still have the related
ioctls marked root-only.
- Apply some power-of-two alignment restrictions to hopefully avoid some
panicing in bad cases of drm_pci_alloc() on FreeBSD.
- Add verbosity to some error handling that I found useful while debugging.
me to match other drivers and avoid ifdeffing. The linux via_drv.c will
be moved from shared-core to linux-core soon by repocopy.
Submitted by: Jake Burkholder <jake@FreeBSD.org> Tested by: unichrome
caller on fb / agp memory alloc and free. Otherwise malicious clients
can register allocations on other clients or free memory used by other
clients which will lead to severe memory manager inconsistensies.
understandable: preinit -> load postinit -> (removed) presetup ->
firstopen postsetup -> (removed) open_helper -> open prerelease ->
preclose free_filp_priv -> postclose pretakedown -> lastclose
postcleanup -> unload release -> reclaim_buffers_locked version ->
(removed)
postinit and version were replaced with generic code in the Linux DRM
(drivers now set their version numbers and description in the driver
structure, like on BSD). postsetup wasn't used at all. Fixes the savage
hooks for initializing and tearing down mappings at the right times.
Testing involved at least starting X, running glxgears, killing
glxgears, exiting X, and repeating.
Tested on: FreeBSD (g200, g400, r200, r128) Linux (r200, savage4)
driver's preinit routine, and by using DRM_COPY_TO_USER_IOCTL when
copying out to an ioctl's data pointer. Pulled from the latest version
of my drm-hook-rename.diff and only compile-tested after that.
code duplication, and it also hands you the map pointer so you don't
need to re-find it.
- Remove the permanent maps flag. Instead, for register and framebuffer
maps, we always check whether there's already a map of that type and
offset around. Move the Radeon map initialization into presetup (first
open) so it happens again after every takedown.
- Remove the split cleanup of maps between driver takedown (last close) and
cleanup (module unload). Instead, always tear down maps on takedown,
and drivers can recreate them on first open.
- Make MGA always use addmap, instead of allocating consistent memory in
the PCI case and then faking up a map for it, which accomplished nearly
the same thing, in a different order. Note that the maps are exposed to
the user again: we may want to expose a flag to avoid this, but it's
not a security concern, and saves us a lot of code.
- Remove rmmaps in the MGA driver. Since the function is only called during
takedown anyway, we can let them die a natural death.
- Make removal of maps happen in one function, which is called by both
drm_takedown and drm_rmmap_ioctl.
Reviewed by: idr (previous revision) Tested on: mga (old/new/pci dma),
radeon, savage
zero does not mean no privs, instead it grants write access
_DRM_READ_ONLY only applies to non-root users. Problem is only in CVS,
initmaps are not in the kernel yet.
zero does not mean no privs, instead it grants write access
_DRM_READ_ONLY only applies to non-root users. Problem is only in CVS,
initmaps are not in the kernel yet.
This patch adds serveral new ioctls and a new query to get_param query to
support PCI MGA cards.
Two ioctls were added to implement interrupt based waiting. With this
change, the client-side driver no longer needs to map the primary DMA
region or the MMIO region. Previously, end-of-frame waiting was done by
busy waiting in the client-side driver until one of the MMIO registers
(the current DMA pointer) matched a pointer to the end of primary DMA
space. By using interrupts, the busy waiting and the extra mappings are
removed.
A third ioctl was added to bootstrap DMA. This ioctl, which is used by the
X-server, moves a *LOT* of code from the X-server into the kernel. This
allows the kernel to do whatever needs to be done to setup DMA buffers.
The entire process and the locations of the buffers are hidden from
user-mode.
Additionally, a get_param query was added to differentiate between G4x0
cards and G550 cards. A gap was left in the numbering sequence so that,
if needed, G450 cards could be distinguished from G400 cards. According
to Ville Syrjälä, the G4x0 cards and the G550 cards handle
anisotropic filtering differently. This seems the most compatible way
to let the client-side driver know which card it's own. Doing this very
small change now eliminates the need to bump the DRM minor version
twice.
http://marc.theaimsgroup.com/?l=dri-devel&m=106625815319773&w=2
A number of ioctl handlers in linux-core were also modified so that they
could be called in-kernel. In these cases, the in-kernel callable
version kept the existing name (e.g., drm_agp_acquire) and the ioctl
handler added _ioctl to the name (e.g., drm_agp_acquire_ioctl).
This patch also replaces the drm_agp_do_release function with
drm_agp_release. drm_agp_release (drm_core_agp_release in the previous
patch) is very similar to drm_agp_do_release, and I saw no reason to
have both.
This commit *breaks the build* on BSD. Eric said that he would make the
required updates to the BSD side soon.
Xorg bug: 3259 Reviewed by: Eric Anholt
There were two problems. First, the 'warp' and 'primary' pointers weren't
cleared, so mga_do_cleanup_dma, which gets called multiple times, would
try to ioremapfree them multiple times. This resulted in the new error
messages to syslog. The second problem was the, since the dev_private
structure isn't reallocated and cleaned out in mga_do_init_dma, when
the server is reloaded idle-waits would wait for impossible values.
I have given this patch some more riggorous testing. This includes:
- Load module, start server, run GL app, stop server, unload module.
- Load module, start server, run GL app, stop server, unload module, reload
module, restart server, run GL app.
- Load module, start server, run GL app, stop server, restart server, run
GL app, stop server, unload module.
In all three cases, everything worked as expected. Please let me know if
there are any further regressions with this patch.
Xorg bug: 3408 Reported by: Chris Rankin
the driver is loaded and is always expected to be around, it should
only be deallocated when the driver is unloaded.
Xorg bug: #3408 Reported by: Chris Rankin
There's two choices when fb is or isn't loaded as we treat ourselves as a
PCI driver in the latter case.
If we are a PCI driver, then register the suspend/resume functions
directly. If not, then we register as a sysdev and pick up the
suspend/resume actions and pump them down into a generic *power
function.
It'll be nice when this little mess is sorted out with regard to being a
real PCI driver ;-/
that a device absolutely is, absolutely is not, or may or may not be
AGP. Modify the i915 DRM to use this to force all i9x5 devices to be
"AGP" (even the PCI-e devices).
Reported by: Lukas Hejtmanek
two routines (one for G200 and one for G400) were replaced with static
const variables and a single function that returns the correct size.
The code to generate an error if the allocated WARP region is too small
was refactored from mga_warp_install_{g200,g400}_microcode to
mga_wrap_install_microcode.
mga_warp_microcode_size is global to the MGA DRM because it will soon be
used by code in another file.
is now allocated (and partially filled in) by the new
mga_driver_preinit function.
This allows the driver to detect the type of card (i.e., G200 class vs.
G400 class) on its own. The chipset value passed to mga_dma_init is now
ignored. This same technique is used by the radeon DRM.
As a result of this, mga_driver_pretakedown was converted to
mga_driver_postcleanup. This routine gets called in some other places
than might be expected, and it sets the dev_private pointer to NULL.
That little gem took over an hour to track down. :(
platform-specific drm_device_is_agp function. Added implementation of
this function the the Linux-specific portion of the MGA driver to
detect PCI G450 cards. Added code to the Linux-specific portion of the
generic DRM layer to not initialize AGP infrastructure if the card is
not AGP (this matches what already existed in BSD).
Bumped the driver date and the driver patch-level for MGA.
This mostly fixes bugzilla #3248. The BSD side still needs an
implementation of mga_driver_device_is_agp.
with IOMMUs and such. There is one usage of the forbidden vtophys()
left in drm_scatter.c which will be fixed up soon. This required a KPI
change for drm_pci_alloc/free() to return/use a drm_dma_handle_t that
keeps track of os-specific bits, rather than just passing around the
vaddr/busaddr/size.
Submitted by: Tonnerre Lombard (partially) Tested on: FreeBSD: Rage128
AGP/PCI Linux: Savage4 AGP/PCI
1) Security fix: Stopped possible MMIO access to PCI DMA area for the
unichrome Pro.
2) Fixed an odd cpu usage problem by padding small AGP DMA submissions.
Bumped patchlevel.
New PCI command parser. Moved from via_dma.c to via_verifier.c so functions
with similar functionality are close to eachother.
Moved video related functions to via_video.c, which might be extended in
the future, as new video functionality is added.
New device-specific generic IRQ IOCTL, similar to the general VBLANK IOCTL,
but with support for multiple device IRQ sources and functionality.
Support for Unichrome Pro PM800/CN400 video DMA commands in verifier and
PCI parser.
Support for Unichrome Pro PM800/CN400 HQV IRQs in the new generic IRQ
IOCTL.
Bumped minor. New version 2.6.0.
1. Initialize futex locks to zero on device init.
2. Remove some stray defines from via_drm.h
3. Prepare via_drm.h for drm client inclusion. The goal is to share a
common file with common definitions.
4. Sync shared / shared-core via_drm.h
5. Bump minor, because of the futex lock initialization.
after ~5min: buffer aging was subtly broken. Part of this may have also
affected vertex DMA buffer aging and client-side texture heap aging,
though with less fatal consequences. Bumped minor version and driver
date.
command and vertex DMA don't work at the same time. Command DMA
performance is superior and works with all vertex formats. Bumped minor
version and driver date.
event counters in the SAVAGE_EVENT_EMIT/WAIT ioctls. This is needed for
reliable client-side texture heap aging. Slightly simplified DMA buffer
aging while at it. Bumped minor version and driver date.
privileges on Radeon hardware. Essentially, a malicious program could
submit a packet containing an offset (possibly in main memory) to be
rendered from/to, while a separate thread switched that offset in
userspace rapidly between a valid value and an invalid one.
radeon_check_and_fixup_offset() would pull the offset in from user
space, check it, and spit it back out to user space to be copied in
later by the emit code. It would sometimes catch the bad value, but
sometimes the malicious program could modify it after the check and get
an invalid offset rendered from/to.
Fix this by allocating a temporary buffer and copying the data in at once.
While here, make the cliprects stuff not do the VERIFYAREA_READ and
COPY_FROM_USER_UNCHECKED gymnastics, avoiding a lock order reversal on
FreeBSD. Performance impact is negligible -- no difference on r200 to
~1% improvement on rv200 in quake3 tests (P4 1Ghz, demofour at
1024x768, n=4 or 5).
FreeBSD. Add drm_get_resource_{start|len} so linux-specific stuff
doesn't need to be in shared code.
- Fix mach64 build by using __DECONST to work around passing a const
pointer to useracc, which is unfortunately not marked const.
- Get rid of a lot of maplist code by not having dev->maplist be a pointer,
and by sticking the link entries directly in drm_local_map_t rather
than having a separate structure for the linked list.
- Factor out map uninit and removal into its own routine, rather than
duplicating in both drm_takedown() and drm_rmmap().
- Hook up more driver functions, and correct FreeBSD-specific bits of
radeon_cp.c, making radeon work.
- Baby steps towards using bus_space as we should.
Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX for ELTs support in
the _savage_render_stage of the 3D driver
Bumped minor version and driver date
The attached patch adds a new buffer type DRM_FB_BUFFER. It works like AGP
memory but uses video memory.
From: austinyuan@viatech.com.cn (fd.o bug 1668) Signed-off-by: Dave Airlie
<airlied@linux.ie>
passed to the cmdbuf ioctl (try xeyes on top of glxgears ;-)
Tightened the texture state check
Bumped Savage DRM version to 2.1.0 so that DRI driver can (theoretically)
depend on the DRM to manage the scissor registers
Release video futexes when context is destroyed (This was previously done
by the X server).
Added New Unichrome Pro VIDEO DMA commands to the verifier.
Added Quiescent heavyweight lock mode.
implementation errors). Direct hardware (MMIO, BCI) access is no longer
needed in the Mesa driver. Bumped version to 2.0.0. Corresponding
changes to the DDX and Mesa drivers are being committed.
bug in the cmdbuf_size ioctl. Modified ring-buffer jump code AGAIN, due
to new oddities discovered on the Unichrome Pro with faster processors.
Bumped patchlevel and driver date.
1. Improved security check of AGP texture adresses.
2. Hopefully last fix of ring-buffer jump oddities.
3. Added ioctl to check available space and command regulator lag in
ring-buffer. This is needed for 3D application responsiveness.
1. The command verifier was never initialized in the non-core source tree.
2. Check added that the AGP ring buffer has been initialized before
accepting command buffer.
3. Free space check in the AGP buffer is moved to after command
verification, which is more optimal in most cases.
drivers/char/drm/sis_ds.h:88:12: warning: dubious one-bit signed
bitfield drivers/char/drm/sis_ds.h:89:16: warning: dubious one-bit
signed bitfield
Signed-off-by: Randy Dunlap <rddunlap@osdl.org> Signed-off-by: Dave Airlie
<airlied@linux.ie>
driver. It can now handle the 3D OpenGL commands from the Mesa
unichrome driver.
Added vsync frequency detection support. This will be used in the future
for XvMC and better frame timing.
Bumped minor version number and driver date.
code. Remove the "drv" from sisdrv, as it's unnecessary. Use the
drm_pci functions in i915 instead of per-os implementations of the
same. Avoid whitespace within fields in drm_pciids.txt (one of the r300
definitions), since it breaks the bsd pciids script. Tested on sis,
mga, r128. i915 needs more work.
DRM_IOCTL_VIA_DMA_INIT DRM_IOCTL_VIA_CMDBUFFER DRM_IOCTL_VIA_FLUSH
The first ioctl sets up an area in AGP memory that will be used as the ring
buffer. The second ioctl copies a command buffer from user space memory
to the ring buffer. The third ioctl waits for engine idle until it
returns.
The motivation for this patch is to avoid the wait for engine idle call
before each buffer flush in the current DRI driver. With this patch,
the DRI driver can continue to flush its buffer as long as there is
free space in the ring buffer.
This patch adds an additional copy operation on the command buffer. This
buffer copying is necessary to support multiple DRI clients rendering
simultaneously. Otherwise, more CPU time will be spent in the busy loop
waiting for engine idle between DRI context switch. Even in the single
client case, the tradeoff is reasonable in comparision to the kernel
call to check for free buffer space for the client to render directly
to the ring buffer.
2. Big change to the XvMC part of the SAREA. OpenGL clients will not suffer
from this, and via XvMC is still alpha. Needed to make future additions
to XvMC (More decoders and overlays) possible.
3. Bumped version number to 1.3.0.
allows the mesa drivers to use a single definition of the DRM
sarea/IOCTLS located in the drm driver directory. Adjustments were made
to the 2D drivers to not include these changes. Changes to the mesa
copy of DRM were copied to the DRI copy. XFree86 bug: Reported by:
Submitted by: Reviewed by: Obtained from:
a busid that doesn't correspond to the device the DRM is attached to.
This is a breaking of backwards-compatibility only for the
multiple-DRI-head case with X Servers that don't use interface 1.1.
- Move irq_busid to drm_irq.h and make it only return the IRQ for the
current device. Retains compatibility with previous X Servers, cleans
up unnecessary code. This means no irq_busid on !__HAVE_IRQ, but can be
changed if necessary.
- Bump interface version to 1.2. This version when set signifies that the
control ioctl should ignore the irq number passed in and enable the
interrupt handler for the attached device. Otherwise it errors out when
the passed-in irq is not equal to the device's.
- Store the highest version the interface has been set to in the device.
- Fix a recursion on DRM_LOCK in irq_uninstall on FreeBSD. This leaves
irq_uninstall being done without the lock in some cases, but it was
racey anyways.
the 2D driver initializes MC_FB_LOCATION and related registers sanely
the DRM deduces the layout from these registers
clients use the new SETPARAM ioctl to tell the DRM where they think the
framebuffer is located in the card's address space
the DRM uses all this information to check client state and fix it up if
necessary
This is a prerequisite for things like direct rendering with IGP chips and
video capturing.
server or client to notify the DRM that it expects a certain version of
the device dependent or device independent interface. If the major
doesn't match or minor is too large, EINVAL is returned. A major of -1
means that the requestor doesn't care about that portion of the
interface. The ioctl returns the actual versions in the same struct.
- Introduce DRM DI interface version 1.1. If the server requests version
1.1, then the DRM sets the unique itself according to the busid of the
device it probed, which may then be accessed as normal using getunique.
- Request version 1.1 in libdrm's drmOpenByBusID, allowing the X Server to
request based on a BusID. Introduce a wrapper for DRM_IOCTL_SET_VERSION
and bump libdrm minor version.
- Pass the busid in DRIScreenInit if libdrm can handle both a busid and
name. This allows drmOpenByBusID to be used to find the DRM instead of
just the driver name, which allows us in the future to tie a DRM more
strongly to the device it probed to. Introduce a function
DRICreatePCIBusID which creates a busid in the form pci:oooo:bb:dd.f
similar to linux's pci_name() function. This matches the format used by
the DRM in version 1.1. libdrm knows how to match both this format and
the old PCI🅱️d:f format.
- Use the new DRICreatePCIBusID function in the *_dri.c to request the new,
more exact busid format.
from __HAVE_DMA. This will be useful for adding vblank sync support to
sis and tdfx. Rename dma_service to irq_handler, which is more
accurately what it is.
- Fix the #if _HAVE_DMA_IRQ in radeon, r128, mga, i810, i830, gamma to have
the right number of underscores. This may have been a problem in the
case that the server died without doing its DRM_IOCTL_CONTROL to
uninit.
just a single instance. Moved the PCI ID lists from <card>_drv.c in BSD
to <card>.h. The PCI ID lists include a driver private field, which may
be used by drivers for chip family or other information. Based on work
by jonsmirl.
- Make tdfx_drv.c and tdfx.h match other drivers.
- Fixed up linking of sis shared files.
Tested with Radeon and SiS on Linux and FreeBSD, including a Linux setup
with
2 SiS cards in a machine, but only one head being used (with DRI)
allocate framebuffer memory without sisfb, and a new ioctl to be used
by the X Server which tells the DRM what region of framebuffer memory
to allocate from. Also fixes a possibility to panic the kernel I
believe. Tested on linux with sisfb and FreeBSD (without sisfb) with
new DRI only.
2.5.0. It still has some issues, including a flicker in the fps meter
in tuxracer and I've seen garbage left behind after moving/closing
windows. However, it's usable. Add the Option "EnablePageFlip" "YES" to
use it.
DRM_*MEMORYBARRIER we had were related to an MMIO space. This means
arch-specific code on the BSDs, unfortunately. Also add
DRM_MEMORYBARRIER() and change the DRM_READMEMORYBARRIER()s that used
to be read/write barriers to it.
irq handler in DRM(irq_install). Modify all drivers to ensure irq
handler is removed before cleanup and cleanup is called at takedown.
Remove unused buffer private struct fields in i810, i830. Check for
lock on init/cleanup in all drivers except i810/i830. The current DDX
for i810 and i830 doesn't hold the lock on kernel init (FIXME?).
use correct address for ring read pointer writeback (yes, we seem to have
been running with bogus values for the ring read pointer, which
'worked' because the return value of radeon_wait_ring() is never
checked and the ring usually never fills up)
David Airlie
Matthieu Castet
Jesse Barnes
Jakob Bornecrantz
Oliver McFadden
Ben Skeggs
Dave Airlie
Thomas Hellstrom
Eric Anholt
Stephane Marchesin
Nian Wu
Patrice Mandin
Nian Wu
B. Rathmann
Wang Zhenyu
Aapo Tahkola
Michel Dänzer
Ben Skeggs
Zou Nan hai
Jeremy Kolb
Dave Jones
Matthieu Castet
Haihao Xiang
Keith Packard
Ben Skeggs
Dave Airlie
Dave Airlie
Michael Karcher
Roland Scheidegger
George Sapountzis
Felix Kühling
Anish Mistry
Roland Scheidegger
Dave Airlie
Alan Hourihane
Adam Jackson
Thomas Hellstrom
Keith Packard
Brian Paul
Eric Anholt
Adam Jackson
Aapo Tahkola
Thomas Hellstrom
Keith Whitwell
Alan Hourihane
Ian Romanick
Vladimir Dergachev
Jon Smirl
Michel Daenzer
Jose Fonseca
Ville Syrjala
Erdi Chen
Leif Delgass
David Dawes